TECHNICAL FIELD

The present disclosure relates to wireless communications, and in particular, to mitigation of memory effects in a power amplifier such as an integrated Complementary Metal Oxide Semiconductor (CMOS) power amplifier.

BACKGROUND

The Third Generation Partnership Project (3GPP) has developed and is developing standards for Fourth Generation (4G) (also referred to as Long Term Evolution (LTE)) and Fifth Generation (5G) (also referred to as New Radio (NR)) wireless communication systems. Such systems provide, among other features, broadband communication between network nodes, such as base stations, and mobile wireless devices (WD), as well as communication between network nodes and between WDs. Sixth Generation (6G) wireless communication system standards are in development.

Power Amplifiers, memory effects and Digital/Analog Predistortion

Radio frequency power amplifiers (PAs) are inherently nonlinear, especially when they are operating with high efficiency. Therefore, PAs typically must be linearized to meet linearity requirements in cellular systems. The non-linearity of a PA might otherwise ruin the quality of the transmitted signal, by providing high error vector magnitude (EVM), and/or disturb communication in neighboring frequency channels, commonly measured by adjacent channel leakage ratio (ACLR). Typically, linearization of the PA is performed using digital predistortion (DPD), which can compensate not only for instantaneous nonlinearities, but also for memory effects. The PA can also be linearized using analog predistortion, which in many ways works just like digital pre-distortion but implemented in the analog domain.

Memory effects in a PA occur when the output of the PA is dependent not only on the present input signal but also on previous ones. The PA then has an internal state that depends on the previous input signals, which affects the output signal. Naturally, memory effects lead to distortion, as an ideal amplification of the input signal should not depend on previous input signals.

The internal states, i.e. memories, in electronic circuits can be either electrical, thermal or mechanical. Normally, it is only the first two that are relevant for PAs and therefore mechanical memories are disregarded here.

Electrical Memories in Power Amplifiers

The energy stored in the electric and magnetic fields in capacitors and inductors respectively, acts as a memory in an electronic system. The voltage over a capacitor and the current through an inductor depends on all previous values of the current and voltage respectively. Capacitors and inductors store information about previous states and together with resistors they produce different time constants that determine how long it takes for the circuit to forget old states. These time constants have a large impact on the memory effects, and thereby the distortion of the circuit. Moreover, the time constants play a key role in attempts to linearize a PA with memory effects.

Thermal Memories in Power Amplifiers

Thermal memories interact with power amplification since the behavior of electrical components in general, and transistors in particular, depend on temperature. As the PA dissipates power in the form of heat, due to non-ideal efficiency, the PA heats itself and its surroundings. Thermal energy is stored in the mass, for instance in the silicon substrate close to the transistor, and in the package and the heatsink. The temperature, and the distribution of it, represents a memory of preceding power dissipation. Similar to electrical memories, time constants for how fast the temperature rises and cools off exist. Time constants depend on a lot of things, but worth mentioning are material constants such as heat capacity and conductivity, but also on transistor layout on the silicon die, the die thickness, the package, and the heat sink.

Digital pre-distorters (DPDs) can compensate for memory effects by adjusting the input signal based on previous input signals. To do this effectively, the DPD must remember earlier input signals for a time duration proportional to the time constants of the PA memory effects to compensate for. This means that if the PA has a long time constant for a memory effect that needs to be compensated for, then the DPD must be equipped with a long digital memory. The size of the digital memory will be proportional to the memory length in time multiplied by the sample rate. For growing bandwidth, and with high over-sampling rates, as in modern cellular systems, such as 5G or 6G, this increases digital hardware cost, size, and power consumption.

Analog predistortion typically implements memory using delay lines, which also become very circuit board or integrated circuit real estate area-consuming and power-consuming as the delay time is increased.

To summarize, both digital and analog predistortion can effectively compensate for PA memory effects with short time constants, but become very complex, power consuming and hardware intensive to compensate for memory effects with long time constants. This is especially true for wide bandwidth signals that, for representation of adjacent channels, or to increase frequency distance to repeated spectrum, are represented a with high oversampling ratio.

SUMMARY

Some embodiments advantageously provide methods, systems, and apparatuses for mitigation of memory effects in a power amplifier.

In some embodiments, the state of electrical and/or thermal memories in the PA are sensed and the sensed states are used to compensate the input signal so that memory effects on the output of the power amplifier are at least partially compensated.

The electrical and/or thermal memory states that are sensed may have significant impact on the PA linearity performance and have long time constants making them difficult to linearize with conventional pre-distortion. Two major contributors to memory effects in a PA that are accessible for sensing are:

1) The local PA supply voltage that is assumed to vary and have memory due to the PA consuming a signal dependent current from a supply with resonances of energy storing parasitic supply net inductance and decoupling capacitors; and

2) Local die temperature due to PA power dissipation.

In some embodiments, the state of electrical and/or thermal memories in a PA are sensed to adjust the input signal. A multi-dimensional memory-less pre-distorter can then be used adjust the input signal and mitigate the memory effects associated with the sensed states. Some embodiments may result in at least one of: a less complicated DPD, a lower DPD memory requirement, improved PA output linearity, lower cost, less hardware, lower power consumption. Lower power consumption may be achieved in the DPD as well as in the PA. In some embodiments, methods described herein for compensating for memory effects, may also compensate for memory state changes caused by external factors such as adjacent circuitry disturbing the supply voltage and/or temperature. The effects of such external factors are not captured by conventional pre-distortion.

According to one aspect, a method of compensating for memory effects in a power amplifier in a transmitter is provided. The method includes sensing memory states of the power amplifier, a memory state being at least one of an electrical state of an electrical memory of the power amplifier and a thermal state of a thermal memory of the power amplifier. The method also includes predistorting an input signal input to the transmitter based at least in part on the sensed memory states of a memory of the power amplifier to produce a compensated transmitter output signal.

According to this aspect, in some embodiments, the method includes comprising compensating for long term memory effects based at least in part on the sensed memory states, the long term memory effects corresponding to a first time constant. In some embodiments, the first time constant is based at least in part on a rate of at least one of increase and decrease in heat of the thermal memory of the power amplifier. In some embodiments, the first time constant is based at least in part on a rate of at least one of increase and decrease of stored energy in the electrical memory of the power amplifier. In some embodiments, the method also includes compensating for short term memory effects, the short term memory effects corresponding to a second time constant shorter than the first time constant. In some embodiments, the long term memory effects are determined based at least in part on the sensed memory states and the short term memory effects are based at least in part on a supply voltage. In some embodiments, the method also includes compensating for the long term memory effects and the short term memory effects by applying an output of a non-linear function having at least two inputs, the at least two inputs corresponding to the input signal and at least one sensed memory state. In some embodiments, the method also includes determining the non-linear function based at least in part on an inverse of a transfer function having amplitude and phase. According to another aspect, a transmitter includes a power amplifier having a memory and memory sensing circuitry. The memory sensing circuitry is configured to sense memory states of the memory, a memory state being at least one of an electrical state of an electrical memory of the power amplifier and a thermal state of a thermal memory of the power amplifier. The transmitter further includes a digital predistorter in communication with the memory sensing circuitry and configured to predistort an input signal input to the transmitter based at least in part on the sensed memory states of a memory of the power amplifier to produce a compensated transmitter output signal.

According to this aspect, in some embodiments, the digital predistorter is configured to compensate for long term memory effects based at least in part on the sensed memory states, the long term memory effects corresponding to a first time constant. In some embodiments, the first time constant is based at least in part on a rate of at least one of increase and decrease in heat of the thermal memory of the power amplifier. In some embodiments, the first time constant is based at least in part on a rate of at least one of increase and decrease of stored energy in the electrical memory of the power amplifier. In some embodiments, the digital predistorter is further configured to compensate for short term memory effects, the short term memory effects corresponding to a second time constant shorter than the first time constant. In some embodiments, the long term memory effects are determined based at least in part on the sensed memory states and the short term memory effects are based at least in part on a supply voltage. In some embodiments, the digital predistorter is configured to compensate for the long term memory effects and the short term memory effects by determining an output of a non-linear function having at least two inputs, the at least two inputs corresponding to the input signal and at least one sensed memory state. In some embodiments, the digital predistorter is configured to determine the non-linear function based at least in part on an inverse of a transfer function having amplitude and phase.

According to yet another aspect, a digital predistorter is configured to compensate for memory effects in a power amplifier of a radio transmitter. The digital predistorter includes: memory sensing circuitry configured to sense memory states of the power amplifier, a memory state being at least one of an electrical state of an electrical memory of the power amplifier and thermal state of a thermal memory of the power amplifier; and processing circuitry in communication with the memory sensing circuitry and configured to predistort an input signal input to the radio transmitter based at least in part on the sensed memory states of the memory of the power amplifier to produce a compensated radio transmitter output signal.

According to this aspect, in some embodiments, the predistorting includes compensating for long term memory effects based at least in part on the sensed memory states, the long term memory effects corresponding to a first time constant. In some embodiments, the first time constant is based at least in part on a rate of at least one of increase and decrease in heat of the thermal memory of the power amplifier. In some embodiments, the first time constant is based at least in part on a rate of at least one of increase and decrease of stored energy in the electrical memory of the power amplifier .

According to another aspect, a method in a digital predistorter configured to compensate for memory effects in a power amplifier of a radio transmitter is provided. The method includes: sensing memory states of the power amplifier, a memory state being at least one of an electrical state of an electrical memory of the power amplifier and a thermal state of a thermal memory of the power amplifier; and predistorting an input signal input to the radio transmitter based at least in part on the sensed memory states of the memory of the power amplifier to produce a compensated radio transmitter output signal.

According to this aspect, in some embodiments, the predistorting includes compensating for long term memory effects based at least in part on the sensed memory states, the long term memory effects corresponding to a first time constant. In some embodiments, the first time constant is based at least in part on a rate of at least one of increase and decrease in heat of the thermal memory of the power amplifier. In some embodiments, the first time constant is based at least in part on a rate of at least one of increase and decrease of stored energy in the electrical memory of the power amplifier.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete understanding of the present embodiments, and the attendant advantages and features thereof, will be more readily understood by reference to the following detailed description when considered in conjunction with the accompanying drawings wherein:

FIG. l is a schematic diagram of an example network architecture illustrating a communication system according to principles disclosed herein; FIG. 2 is a block diagram of a network node in communication with a wireless device over a wireless connection according to some embodiments of the present disclosure;

FIG. 3 is a block diagram of a radio interface having a power amplifier and compensating circuitry for compensating for memory effects according to principles disclosed herein;

FIG. 4 is a block diagram of a transmitter employing circuitry to compensate for memory effects of a power amplifier according to principles disclosed herein;

FIG. 5 is a flowchart of an example process in a transmitter for mitigation of memory effects in a power amplifier according to some embodiments of the present disclosure; and

FIG. 6 is a flowchart of an example process in a digital predistorter according to some embodiments of the present disclosure;

FIG. 7(a) shows a first example power amplifier circuit topology;

FIG. 7(b) shows a second example power amplifier circuit topology having parasitic elements;

FIG. 8 illustrates a resonance caused by the circuitry of FIG. 7(b);

FIG. 9(a) illustrates amplitude to amplitude variations versus output power for an ideal power supply such as the power supply of FIG. 7(a) and a power supply with resonance such as the power supply of FIG. 7(b);

FIG. 9(b) illustrates amplitude to phase variations versus output power for an ideal power supply such as the power supply of FIG. 7(a) and a power supply with resonance such as the power supply of FIG. 7(b);

FIG. 10 illustrates adjacent channel power versus main channel output power for an ideal power supply and a power supply with resonance;

FIG. 11 illustrates an example output amplitude surface as a function of supply voltage and input signal amplitude;

FIG. 12 illustrates an example output phase surface as a function of supply voltage and input signal amplitude; and FIG. 13 illustrates an example of adjacent channel power versus main channel power for a linear input, a one-dimensional predistorter input and a two-dimensional predistorted input.

DETAILED DESCRIPTION

Before describing in detail example embodiments, it is noted that the embodiments reside primarily in combinations of apparatus components and processing steps related to mitigation of memory effects in a power amplifier. Accordingly, components have been represented where appropriate by conventional symbols in the drawings, showing only those specific details that are pertinent to understanding the embodiments so as not to obscure the disclosure with details that will be readily apparent to those of ordinary skill in the art having the benefit of the description herein.

As used herein, relational terms, such as “first” and “second,” “top” and “bottom,” and the like, may be used solely to distinguish one entity or element from another entity or element without necessarily requiring or implying any physical or logical relationship or order between such entities or elements. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the concepts described herein. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

In embodiments described herein, the joining term, “in communication with” and the like, may be used to indicate electrical or data communication, which may be accomplished by physical contact, induction, electromagnetic radiation, radio signaling, infrared signaling or optical signaling, for example. One having ordinary skill in the art will appreciate that multiple components may interoperate and modifications and variations are possible of achieving the electrical and data communication. In some embodiments described herein, the term “coupled,” “connected,” and the like, may be used herein to indicate a connection, although not necessarily directly, and may include wired and/or wireless connections.

The term “network node” used herein can be any kind of network node comprised in a radio network which may further comprise any of base station (BS), radio base station, base transceiver station (BTS), base station controller (BSC), radio network controller (RNC), g Node B (gNB), evolved Node B (eNB or eNodeB), Node B, multi-standard radio (MSR) radio node such as MSR BS, multi-cell/multicast coordination entity (MCE), relay node, donor node controlling relay, radio access point (AP), transmission points, transmission nodes, Remote Radio Unit (RRU) Remote Radio Head (RRH), a core network node (e.g., mobile management entity (MME), self-organizing network (SON) node, a coordinating node, positioning node, MDT node, etc.), an external node (e.g., 3rd party node, a node external to the current network), nodes in distributed antenna system (DAS), a spectrum access system (SAS) node, an element management system (EMS), etc. The network node may also comprise test equipment. The term “radio node” used herein may be used to also denote a wireless device (WD) such as a wireless device (WD) or a radio network node.

In some embodiments, the non-limiting terms wireless device (WD) or a user equipment (UE) are used interchangeably. The WD herein can be any type of wireless device capable of communicating with a network node or another WD over radio signals, such as wireless device (WD). The WD may also be a radio communication device, target device, device to device (D2D) WD, machine type WD or WD capable of machine to machine communication (M2M), low-cost and/or low-complexity WD, a sensor equipped with WD, Tablet, mobile terminals, smart phone, laptop embedded equipped (LEE), laptop mounted equipment (LME), USB dongles, Customer Premises Equipment (CPE), an Internet of Things (loT) device, or a Narrowband loT (NB-IOT) device etc.

Also, in some embodiments the generic term “radio network node” is used. It can be any kind of a radio network node which may comprise any of base station, radio base station, base transceiver station, base station controller, network controller, RNC, evolved Node B (eNB), Node B, gNB, Multi-cell/multicast Coordination Entity (MCE), relay node, access point, radio access point, Remote Radio Unit (RRU) Remote Radio Head (RRH).

Note that although terminology from one particular wireless system, such as, for example, 3GPP LTE and/or New Radio (NR), may be used in this disclosure, this should not be seen as limiting the scope of the disclosure to only the aforementioned system. Other wireless systems, including without limitation Wide Band Code Division Multiple Access (WCDMA), Worldwide Interoperability for Microwave Access (WiMax), Ultra Mobile Broadband (UMB) and Global System for Mobile Communications (GSM), may also benefit from exploiting the ideas covered within this disclosure.

Note further, that functions described herein as being performed by a wireless device or a network node may be distributed over a plurality of wireless devices and/or network nodes. In other words, it is contemplated that the functions of the network node and wireless device described herein are not limited to performance by a single physical device and, in fact, can be distributed among several physical devices.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Some embodiments are directed to mitigation of memory effects in a power amplifier by sensing states of memory of the power amplifier, feeding the sensed states back to the digital predistorter and predistorting an input signal to be amplified by the power amplifier based at least in part on the sensed states. Referring now to the drawing figures, in which like elements are referred to by like reference numerals, there is shown in FIG. 1 a schematic diagram of a communication system 10, according to an embodiment, such as a 3 GPP -type cellular network that may support standards such as LTE and/or NR (5G), which comprises an access network 12, such as a radio access network, and a core network 14. The access network 12 comprises a plurality of network nodes 16a, 16b, 16c (referred to collectively as network nodes 16), such as NBs, eNBs, gNBs or other types of wireless access points, each defining a corresponding coverage area 18a, 18b, 18c (referred to collectively as coverage areas 18). Each network node 16a, 16b, 16c is connectable to the core network 14 over a wired or wireless connection 20. A first wireless device (WD) 22a located in coverage area 18a is configured to wirelessly connect to, or be paged by, the corresponding network node 16a. A second WD 22b in coverage area 18b is wirelessly connectable to the corresponding network node 16b. While a plurality of WDs 22a, 22b (collectively referred to as wireless devices 22) are illustrated in this example, the disclosed embodiments are equally applicable to a situation where a sole WD is in the coverage area or where a sole WD is connecting to the corresponding network node 16. Note that although only two WDs 22 and three network nodes 16 are shown for convenience, the communication system may include many more WDs 22 and network nodes 16.

Also, it is contemplated that a WD 22 can be in simultaneous communication and/or configured to separately communicate with more than one network node 16 and more than one type of network node 16. For example, a WD 22 can have dual connectivity with a network node 16 that supports LTE and the same or a different network node 16 that supports NR. As an example, WD 22 can be in communication with an eNB for LTEZE-UTRAN and a gNB for NR/NG-RAN.

A network node 16 (eNB or gNB) and/or a WD 22 may be configured to include memory sensing circuitry 24, 26 which is configured to sense memory states of the power amplifier, a memory state being at least one of an electrical state of an electrical memory of the power amplifier and a thermal state of a thermal memory of the power amplifier.

Example implementations, in accordance with an embodiment, of the WD 22 and network node 16 discussed in the preceding paragraphs will now be described with reference to FIG. 2.

The communication system 10 includes a network node 16 provided in a communication system 10 and including hardware 28 enabling it to communicate with the WD 22. The hardware 28 may include a radio interface 30 for setting up and maintaining at least a wireless connection 32 with a WD 22 located in a coverage area 18 served by the network node 16. The radio interface 30 may be formed as or may include, for example, one or more RF transmitters, one or more RF receivers, and/or one or more RF transceivers. The radio interface 30 includes an array of antennas 34 to radiate and receive signal(s) carried by electromagnetic waves. In the embodiment shown, the hardware 28 of the network node 16 further includes processing circuitry 36. The processing circuitry 36 may include a processor 38 and a memory 40. In particular, in addition to or instead of a processor, such as a central processing unit, and memory, the processing circuitry 36 may comprise integrated circuitry for processing and/or control, e.g., one or more processors and/or processor cores and/or FPGAs (Field Programmable Gate Array) and/or ASICs (Application Specific Integrated Circuitry) adapted to execute instructions. The processor 38 may be configured to access (e.g., write to and/or read from) the memory 40, which may comprise any kind of volatile and/or nonvolatile memory, e.g., cache and/or buffer memory and/or RAM (Random Access Memory) and/or ROM (Read-Only Memory) and/or optical memory and/or EPROM (Erasable Programmable Read-Only Memory).

Thus, the network node 16 further has software 42 stored internally in, for example, memory 40, or stored in external memory (e.g., database, storage array, network storage device, etc.) accessible by the network node 16 via an external connection. The software 42 may be executable by the processing circuitry 36. The processing circuitry 36 may be configured to control any of the methods and/or processes described herein and/or to cause such methods, and/or processes to be performed, e.g., by network node 16. Processor 38 corresponds to one or more processors 38 for performing network node 16 functions described herein. The memory 40 is configured to store data, programmatic software code and/or other information described herein. In some embodiments, the software 42 may include instructions that, when executed by the processor 38 and/or processing circuitry 36, causes the processor 38 and/or processing circuitry 36 to perform the processes described herein with respect to network node 16. For example, radio interface 30 of the network node 16 may include memory sensing circuitry 24 which is configured to sense memory states of a power amplifier of the radio interface 30, a memory state being at least one of an electrical state of an electrical memory of the power amplifier and a thermal state of a thermal memory of the power amplifier. A more detailed block diagram of the radio interface 30 including the power amplifier is shown in FIG. 4.

The communication system 10 further includes the WD 22 already referred to. The WD 22 may have hardware 44 that may include a radio interface 46 configured to set up and maintain a wireless connection 32 with a network node 16 serving a coverage area 18 in which the WD 22 is currently located. The radio interface 46 may be formed as or may include, for example, one or more RF transmitters, one or more RF receivers, and/or one or more RF transceivers. The radio interface 46 includes an array of antennas 48 to radiate and receive signal(s) carried by electromagnetic waves.

The hardware 44 of the WD 22 further includes processing circuitry 50. The processing circuitry 50 may include a processor 52 and memory 54. In particular, in addition to or instead of a processor, such as a central processing unit, and memory, the processing circuitry 50 may comprise integrated circuitry for processing and/or control, e.g., one or more processors and/or processor cores and/or FPGAs (Field Programmable Gate Array) and/or ASICs (Application Specific Integrated Circuitry) adapted to execute instructions. The processor 52 may be configured to access (e.g., write to and/or read from) memory 54, which may comprise any kind of volatile and/or nonvolatile memory, e.g., cache and/or buffer memory and/or RAM (Random Access Memory) and/or ROM (Read-Only Memory) and/or optical memory and/or EPROM (Erasable Programmable Read-Only Memory).

Thus, the WD 22 may further comprise software 56, which is stored in, for example, memory 54 at the WD 22, or stored in external memory (e.g., database, storage array, network storage device, etc.) accessible by the WD 22. The software 56 may be executable by the processing circuitry 50. The software 56 may include a client application 58. The client application 58 may be operable to provide a service to a human or non-human user via the WD 22.

The processing circuitry 50 may be configured to control any of the methods and/or processes described herein and/or to cause such methods, and/or processes to be performed, e.g., by WD 22. The processor 52 corresponds to one or more processors 52 for performing WD 22 functions described herein. The WD 22 includes memory 54 that is configured to store data, programmatic software code and/or other information described herein. In some embodiments, the software 56 and/or the client application 58 may include instructions that, when executed by the processor 52 and/or processing circuitry 50, causes the processor 52 and/or processing circuitry 50 to perform the processes described herein with respect to WD 22. For example, the radio interface 46 of the wireless device 22 may include memory sensing circuitry 26 which is configured to sense memory states of a power amplifier of the radio interface 46, a memory state being at least one of an electrical state of an electrical memory of the power amplifier and a thermal state of a thermal memory of the power amplifier. A more detailed block diagram of the radio interface 46 including the power amplifier is shown in FIG. 4.

In some embodiments, the inner workings of the network node 16 and WD 22 may be as shown in FIG. 2 and independently, the surrounding network topology may be that of FIG. 1.

The wireless connection 32 between the WD 22 and the network node 16 is in accordance with the teachings of the embodiments described throughout this disclosure. More precisely, the teachings of some of these embodiments may improve the data rate, latency, and/or power consumption and thereby provide benefits such as reduced user waiting time, relaxed restriction on file size, better responsiveness, extended battery lifetime, etc. In some embodiments, a measurement procedure may be provided for the purpose of monitoring data rate, latency and other factors on which the one or more embodiments improve.

Having described the general process flow of arrangements of the disclosure and having provided examples of hardware and software arrangements for implementing the processes and functions of the disclosure, the sections below provide details and examples of arrangements for mitigation of memory effects in a power amplifier.

In some embodiments, the DPD 62 has access to multiple signals, the input signal plus one or more state signals, so that the predistortion becomes multi-dimensional. The output signal of the DPD 62 may then be represented by a non-linear function such as a multidimensional polynomial. For the multi-dimensional polynomial, for example, the polynomial order can be different for the different dimensions. An example of such a polynomial with two dimensions, where the orders in the two dimensions are N and M, respectively, is given below.

Examples of the dimensions of a multi-dimensional polynomial may include the input signal envelope, supply voltage at PA, ground voltage at PA, and local die/junction temperature at the PA. A more detailed block diagram of the radio interface 30, 46 is shown in FIG. 3. A transmitter 60 of the radio interface 30, 46 includes a digital predistorter (DPD) 62. The transmitter 60 includes a power amplifier (PA) 64 having memory 66 and the memory sensing circuitry 24, 26. The memory sensing circuitry 24, 26 may include one or more thermal sensors and/or electrical circuitry to sense heat of thermal memory 66 and/or sense energy storage of electrical memory 66. The signals sensed by the memory sensing circuitry 24, 26 are received by processing circuitry 68 of the DPD 62, which utilizes the sensed thermal and/or electrical memory states to determine a predistortion of an input signal that compensates for memory effects of the power amplifier 64.

A block diagram of an architecture of an example embodiment is shown in FIG. 4. The DPD 62 digitally predistorts the I, Q input signal based at least in part on signals from the memory sensing circuitry 24, 26. The signals from the memory sensing circuitry 24, 26 are representative of memory states of the power amplifier 64 and are converted to the digital domain by analog-to-digital converter (ADC) 78. The predistorted signal output by the DPD 62 is converted to an analog signal by digital-to-analog converter (DAC) 72, processed in transmit blocks 74, and amplified by the amplifier 76 of the PA 64. The thermal and/or electrical memory state of the thermal and/or electrical memory 66 are sensed by the memory sensing circuitry 24, 26.

The multidimensional pre-distorter 62 can be either instantaneous or equipped with short memory to compensate for fast changing memory effects that may be most easily compensated for by the DPD 62 without feedback from the memory sensing circuitry 24, 26. The signals that are fed back to the DPD 62 from the memory sensing circuitry 24, 26 may preferably have long time constants, since the long-time-constant signals would require the longest memories for which compensation is difficult using conventional means. This is true for both for analog and digital pre-distorters. Since the quantities that are fed back may be assumed to have long time constants, requirements for speed in the detectors of the memory sensing circuitry 24, 26 and the feedback path may be relaxed, which further simplifies the implementation.

For simplicity of explanation, a two-dimensional pre-distorter, that is based on the input signal and the supply voltage of the power supply is assumed. Both dimensions may be fitted to third order polynomials. To linearize both amplitude and phase, the transfer function for the output amplitude and output phase for the PA 64 may be inverted to find the required predistortion characteristics, and third order two-dimensional polynomials are fitted to describe the functions. A third order polynomial has four coefficients, i.e., n + 1, where n is the order of the polynomial, but a two-dimensional polynomial has, (n + I) ² , which for a two-dimensional third order polynomial evaluates to 16 coefficients. Of the 16 coefficients, 3 will determine terms purely depending on the input amplitude, 3 purely depending on the supply voltage, and 9 will be cross-terms depending on both input amplitude and supply voltage. The last coefficient will be for the constant term. Both amplitude and phase pre-distortion, will each have a 16 coefficient third order two-dimensional polynomial. This might sound complicated, but it is straightforward method, since no estimation of memory states due to previous input signals is required.

FIG. 3 is a flowchart of an example process in a transmitter for compensating for memory effects in a power amplifier 64 of a transmitter 60. One or more blocks described herein may be performed by one or more elements of network node 16 such as by one or more of processing circuitry 36 (including the memory sensing circuitry 24, 26), processor 38, and/or radio interface 30. Network node 16 such as via processing circuitry 36 and/or processor 38 and/or radio interface 30 is configured to sense memory states of the memory, a memory state being at least one of an electrical state of an electrical memory of the power amplifier and a thermal state of a thermal memory of the power amplifier (Block S10). The process also includes predistorting an input signal input to the transmitter 60 based at least in part on the sensed memory states of a memory of the power amplifier to produce a compensated transmitter output signal (Block S12).

In some embodiments, the process includes compensating for long term memory effects based at least in part on the sensed memory states, the long term memory effects corresponding to a first time constant. In some embodiments, the first time constant is based at least in part on a rate of at least one of increase and decrease in heat of the thermal memory of the power amplifier. In some embodiments, the first time constant is based at least in part on a rate of at least one of increase and decrease of stored energy in the electrical memory of the power amplifier. In some embodiments, the process also includes compensating for short term memory effects, the short term memory effects corresponding to a second time constant shorter than the first time constant. In some embodiments, the long term memory effects are determined based at least in part on the sensed memory states and the short term memory effects are based at least in part on a supply voltage. It is noted that, a supply voltage is an example of an electrical state of an electrical memory. In such cases, the sensed supply voltage is therefore an example of a sensed electrical state of the memory. In some embodiments, the process further includes compensating for the long term memory effects and the short term memory effects by applying an output of a non-linear function having at least two inputs, the at least two inputs corresponding to the input signal and at least one sensed memory state. In some embodiments, the process includes determining the non-linear function based at least in part on an inverse of a transfer function having amplitude and phase.

FIG. 4 is a flowchart of an example process in a wireless device 22 according to some embodiments of the present disclosure. One or more blocks described herein may be performed by one or more elements of wireless device 22 such as by one or more of processing circuitry 50 (including the memory sensing circuitry 24, 26), processor 52, and/or radio interface 46. Wireless device 22 such as via processing circuitry 50 and/or processor 52 and/or radio interface 46 is configured to sense memory states of the power amplifier 64, a memory state being at least one of an electrical state of an electrical memory 66 of the power amplifier and a thermal state of a thermal memory 66 of the power amplifier 64 (Block S14). The process also includes predistorting an input signal input to the radio transmitter 60 based at least in part on the sensed memory states of the memory 66 of the power amplifier 64 to produce a compensated radio transmitter output signal (Block SI 6).

In some embodiments, the predistorting includes compensating for long term memory effects based at least in part on the sensed memory states, the long term memory effects corresponding to a first time constant. In some embodiments, the first time constant is based at least in part on a rate of at least one of increase and decrease in heat of the thermal memory 66 of the power amplifier 64. In some embodiments, the first time constant is based at least in part on a rate of at least one of increase and decrease of stored energy in the electrical memory 66 of the power amplifier 64 .

To demonstrate memory effects and how methods disclosed herein may be used, a test bench for a PA, operating at 27 GHz was implemented in a 22 nanometer (nm) FD-SOI CMOS process design kit and depicted in FIG. 7. Note that the power amplifier circuit topology is an example. The power amplifiers to which the method disclosed herein apply are not limited to such topology but apply to other power amplifier circuit topologies. The test bench used exhibited close to ideal biasing of CS and CG transistors, but with a base-band frequency dependent node impedance for the supply voltage. Furthermore, the output resonance tank has a rather low Q-value, due to the 50-ohm load resistor, which makes the node impedance stay virtually constant over the channel bandwidth at the fundamental frequency. At the supply net, a parasitic resonance tank is formed by the parasitic inductance and the decoupling capacitor, which is depicted in FIG. 7(b). This parasitic resonance can to some extent be mitigated, but it is close to impossible to avoid completely and becomes increasingly troublesome, especially for high bandwidth transmit signals.

The base-band resonance, with realistic values of the inductance L _pa rasitic and capacitances Cdecap and Rdeque, occurs at 40 MHz and with a Q-value of 4 for the test circuit of FIG. 7(b). This base-band resonance is shown in the example of FIG. 8.

The PA distortion with and without the memory effects caused by the parasitic supply resonance, are demonstrated in the examples of FIGS. 9 and 10. These figures identify how severe the problem is for the simulated test circuit, where the PA 64 is simulated using a 100 MHz modulated orthogonal frequency division multiplexed (OFDM) signal at 27 GHz. The amplitude to amplitude (AM-AM) and amplitude to phase (AM-PM) variation versus PA output power is shown in FIGS. 9(a) and 9(b), respectively, for an ideal power supply such as shown in FIG. 7(a) and for a power supply with resonance such as shown in FIG. 7(b). Note that there is greater dispersion for the power supply with resonance which dispersion increases for higher PA output power levels. FIG. 10 shows the adjacent channel power (ACPR) for the case without the supply resonance and with the supply resonance. FIGS. 9 (comprised of FIGS. 9(a) and 9(b)) and 10 show that memory effects cause significant distortion at high output power levels, but with virtually no deterioration at low output levels. This may arise from the PA in the test bench being biased high, and for very low output powers the PA may then operate in class A, making the supply current constant regardless of the input signal. This may prevent the PA from injecting baseband frequency current as the signal envelope is modulated. This may otherwise be expected to occur close to the resonance frequency of the parasitic supply resonance. Furthermore, the PA is rather insensitive to supply voltage variations as long as the PA does not compress in output voltage, which it only does for high output power levels. Returning to the example PA of FIG. 7(b), which has the parasitic supply resonance at 40 MHz with a Q-value of 4, as the current consumption of the PA depends on the input amplitude, i.e., the envelope of the input signal, the magnitude of the supply current will be modulated with the bandwidth of the envelope of the modulation. This means that the PA will inject some current at the resonance frequency of the supply net resonance, resulting in a ringing of the supply net. How strong the voltage of the ringing is and its phase position will depend on historical input signals. To compensate for the memory effects that the supply ringing constitutes, method disclosed here may advantageously be employed. The input signal may therefore be adjusted by the DPD 62 depending on the voltage level of the supply. This gives rise to two input signals to the DPD 62: the input IQ-signal s and the detected supply voltage, for which a two-dimensional polynomial may be employed. The first dimension is, as for a regular one-dimensional case, the input envelope, which may be derived directly from the IQ-signal envelope equal to -^/l ² + Q ² . The second dimension includes an extent of an excursion of the PA local supply voltage from the nominal supply. As before, a continuous wave (CW) tone at 27 GHz was used to simulate output magnitude and phase for increasing input amplitude. In the simulation, both input amplitude and supply voltage were swept.

An input amplitude-supply voltage plane for phase and magnitude are depicted in FIGS. 11 and 12. As before, the PA suffering from the parasitic supply resonance shown in FIG. 7(b) was simulated with a 100 MHz, 7 dB peak to average ratio (PAR), modulated OFDM-signal at 27 GHz, both using an undistorted input signal and a pre-distorted input signal. The pre-distorted input signal was achieved from the method described above. In addition, a third case was simulated, where the supply feedback signal representing the memory effect was removed, essentially reducing the two-dimensional third order polynomials to a one-dimensional polynomial. As a measure of the improved linearity of the PA 64 produced by the methods disclosed herein, for the three input signals, the ACPR was plotted versus the main channel power in FIG. 13. For low output power levels, the memory effects do not deteriorate the linearization, and the two-dimensional and one-dimensional pre-distortions may be equally linear. As output signal increases, the memory effects caused by the supply ringing increasingly distorts the output, and for very high output levels the one-dimensional predistortion does not perform better than a completely linear input signal. As will be appreciated by one of skill in the art, the concepts described herein may be embodied as a method, data processing system, computer program product and/or computer storage media storing an executable computer program. Accordingly, the concepts described herein may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects all generally referred to herein as a “circuit” or “module.” Any process, step, action and/or functionality described herein may be performed by, and/or associated to, a corresponding module, which may be implemented in software and/or firmware and/or hardware. Furthermore, the disclosure refers to embodiments that may include a computer program product on a tangible computer usable storage medium having computer program code embodied in the medium that can be executed by a computer. Any suitable tangible computer readable medium may be utilized including hard disks, CD- ROMs, electronic storage devices, optical storage devices, or magnetic storage devices. In some embodiments, certain hardware, such as the digital predistorter 62, may be implemented by dedicated hardware such as an application specific integrated circuit (ASIC).

Some embodiments are described herein with reference to flowchart illustrations and/or block diagrams of methods, systems and computer program products. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer (to thereby create a special purpose computer), special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.

Many different embodiments have been disclosed herein, in connection with the above description and the drawings. It will be understood that it would be unduly repetitious and obfuscating to literally describe and illustrate every combination and subcombination of these embodiments. Accordingly, all embodiments can be combined in any way and/or combination, and the present specification, including the drawings, shall be construed to constitute a complete written description of all combinations and subcombinations of the embodiments described herein, and of the manner and process of making and using them, and shall support claims to any such combination or subcombination.

Abbreviations that may be used in the preceding description include:

AAS Antenna Array

System

ACLR Adjacent Channel Leakage Ratio

ACPR Adjacent Channel Power

ADC Analog to Digital Converter

AM-AM Amplitude to Amplitude

AM-PM Amplitude to Phase

BB Base Band

CG Common Gate

CMOS Complementary Metal Oxide Semiconductor

CS Common Source

DAC Digital to Analog Converter

DPD Digital Predistortion

EVM Error Vector Magnitude

LUT Look Up Table

OFDM Orthogonal Frequency Division Multiplexing

PA Power Amplifier

PAR Peak to Average Ratio

PPA Pre-Power Amplifier

RF Radio Frequency

TX Transmitter

It will be appreciated by persons skilled in the art that the embodiments described herein are not limited to what has been particularly shown and described herein above. In addition, unless mention was made above to the contrary, it should be noted that all of the accompanying drawings are not to scale. A variety of modifications and variations are possible in light of the above teachings without departing from the scope of the following claims.