Title:
NON-VOLATILE MEMORY
Document Type and Number:
WIPO Patent Application WO/2022/074968
Kind Code:
A1
Abstract:
In the present invention, a memory cell includes first and second transistors. A driving circuit includes: a boost circuit configured to generate a boosted voltage on a boost line by boosting a prescribed reference voltage; and an adjustment circuit configured to adjust the boosted voltage by letting an adjustment current corresponding to the boosted voltage flow in from the boost line. The driving circuit supplies the adjusted boosted voltage to the respective gates of the first and second transistors as a read voltage. In a read operation, in which the read voltage is supplied, a signal output circuit outputs a signal associated with a first value or a second value on the basis of the respective drain currents of the first and second transistors.
Inventors:
TAKENAKA SEIJI (JP)
Application Number:
PCT/JP2021/032241
Publication Date:
April 14, 2022
Filing Date:
September 02, 2021
Export Citation:
Assignee:
ROHM CO LTD (JP)
International Classes:
G11C16/08; G11C16/04; G11C16/30
Foreign References:
| JP2008065966A | 2008-03-21 | |||
| JP2005267789A | 2005-09-29 |
Attorney, Agent or Firm:
SANO PATENT OFFICE (JP)
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