Title:
PHASE COMPARISON CIRCUIT AND PLL SYNTHESIZER USING THE SAME
Document Type and Number:
WIPO Patent Application WO/2007/080918
Kind Code:
A1
Abstract:
A phase comparison circuit is provided with a fraction divider (31) for forming a
fraction divisional signal (Svn) by fraction-dividing a clock signal in response to
a control signal from a control circuit (32), a first integer divider (33) for forming
a first integer-dividing signal by integer-dividing the fraction dividing signal
(Svn), a second integer divider (34) for forming a second integer-dividing signal
by integer-dividing a reference clock signal, a first selecting circuit (35)
for selecting either the fraction-dividing signal (Svn) or the first integer-dividing signal
in response to a switching signal, a second selecting circuit (36) for selecting
either the reference clock signal or the integer-dividing signal in response
to a switching signal from a control circuit (32), and a phase comparator (37)
for generating a comparison signal indicative of frequency and phase differences between
output signals from the first and second selecting circuits (35) and (36).
Inventors:
OHTSUKA SHIGEKI (JP)
Application Number:
PCT/JP2007/050230
Publication Date:
July 19, 2007
Filing Date:
January 11, 2007
Export Citation:
Assignee:
THINE ELECTRONICS INC (JP)
OHTSUKA SHIGEKI (JP)
OHTSUKA SHIGEKI (JP)
International Classes:
H03D13/00; H03K5/26; H03L7/197
Foreign References:
| JP2000068828A | 2000-03-03 | |||
| JPH1022824A | 1998-01-23 | |||
| JPH05152946A | 1993-06-18 | |||
| US5920233A | 1999-07-06 | |||
| US2076009A | 1937-04-06 |
Other References:
See also references of EP 1978639A4
Attorney, Agent or Firm:
HASEGAWA, Yoshiki et al. (Ginza First Bldg., 10-6Ginza 1-chome, Chuo-k, Tokyo 61, JP)
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