PLL circuits are widely used circuit building blocks. A few of their applications are tone decoding, demodulation of AM and FM signals, frequency multiplication, frequency synthe- sis, pulse synchronisation of signals from noisy sources and the regeneration of signals without noise. Typically, a PLL comprises a phase detector circuit, an amplifier or charge pump, a filter circuit and a voltage controlled os- cillator. The phase detector circuit detects the phase dif- ference of two signals. One of these signals is a reference signal. The other one is generated in the PLL. The charge pump generates an analog signal with a high current drive suitable for the control of the VCO. The frequency of the VCO is adjusted until the reference signal and the signal which is compared to the reference signal by the phase de- tector are synchronised.

Before the signals provided by the charge pump circuit is fed to the VCO, a DC signal is usually generated in a loop filter circuit. This filter circuit averages the signal provided by the charge pump. The charge pump typically gen- erates two fixed current values of the same amount, but op- posite sign corresponding to the digital 0 and 1 respec- tively provided by the phase detector. A zero current at the input of the VCO usually signifies that the VCO main- tains its frequency.

The signal generated in the PLL and being compared to the reference signal is not necessarily identical with the sig- nal generated by the VCO. For a very common application, the signal of the VCO is firstly divided by a divider and then fed to the phase detector. The VCO therefore generates a frequency which is by a factor given by the inverse of the divider ratio higher than the reference signal (fre- quency multiplication).

In digital PLLs, EXOR gates can be used as phase detectors.

If the reference signal and the signal generated in the PLL do not have a duty factor of 50 % at the beginning, their duty factors are often altered to 50 % before comparison by the phase detector. A duty factor of 50 % is very suitable for EXOR detectors. In this case, the duty factor of the signal generated by the EXOR gate increases linearly with increasing phase difference between the two compared sig- nals and reaches its maximum value of 100 % for a phase difference of 180 degrees and decreases afterwards again. A duty factor of 50 % occurs for a phase difference of 90 degrees. Hence, the charge pump current is zero for a phase difference of 90 degrees after filtering and the phase shift between the reference signal and the signal compared to the reference signal is 90 degrees in steady-state conditions.

Using an EXOR gate as phase detector for example, it is ex- tremely difficult to synchronise both signals if the phase difference between both signals is larger than 180 degrees because the relationship between the phase difference sig- nal and the phase difference is no more linear. Such large phase differences can for example occur if the divider ra- tio is changed, the frequency of the reference signal changes or mechanical stress such as vibrations or shocks is applied to the PLL circuit. The time it takes until the

phase-locked loop reaches its steady-state conditions, i. e. the lock time, can take relatively long. Therefore, differ- ent means and methods for reducing the lock time have been developed in the state of the art.

The US 6,265, 902 discloses a digital phase detector having a slip detection circuit for detecting and compensating for a cycle slip. This digital phase detector is especially suited for signals whose duty factor is not 50 %. However, the phase detector is rather complicated as it implies the detection of the leading and trailing edges of both signals compared by the phase detector.

The US 6,265, 362 discloses an apparatus that aides in the locking of a phase-locked loop to the correct frequency and that aides in recovering from loss of lock conditions. A disadvantage of the apparatus is that the PLL circuit is rather complex as it requires two slip detectors and a counter.

The US 6, 441, 691 discloses a further phase detector for a PLL circuit. This phase detector comprises two input cir- cuits, a reset circuit, and two frequency dividers. Disad- vantageously, the PLL circuit is as well rather complex.

The object underlying the present invention is to provide a phase-locked loop circuit enabling quick lock times without the requirement of complex circuitry. Further, a corre- sponding controller and an advantageous method for control- ling a frequency modulator are to be provided.

In one aspect of the present invention, a phase-locked loop circuit comprising: a voltage controlled oscillator gener-

ating oscillator signals with frequencies dependent on in- put signals applied to said voltage controlled oscillator; a frequency modulator receiving input signals and generat- ing frequency modulated signals; a phase detector providing phase difference signals on the basis of the phase differ- ence between said frequency modulated signals and further signals; a linear range detector detecting whether said phase detector is in a linear range by analysis of said frequency modulated signals and said further signals and generating linear range signals ; is characterised in that a controller receiving said linear range signals controls the frequency of said frequency modulated signals by a fre- quency adjustment so that said phase detector gets back into said linear range after a change in the frequency of the frequency modulated signals to a desired frequency.

An advantage of the present invention is that the lock time can be shortened because the phase detector operates nearly exclusively in the linear range.

A further advantage is that the shortening of the lock time can be achieved without the requirement of complex cir- cuitry.

In one feature of the present invention, said linear range detector has two outputs for said linear ranges signals, wherein combinations of said linear range signals indicate whether said frequency adjustment is to be performed and whether said frequency adjustment consists of a frequency increase or frequency decrease.

In a further feature of the present invention, said further signals are oscillator signals and said input signals re- ceived by said frequency modulator are reference signals.

This feature covers a phase-locked loop circuit for which said frequency modulator receives the reference signals and provides said frequency modulated signals on the basis of said reference signals at the output.

In an alternative feature of the present invention, said further signals are reference signals and said input sig- nals received by said frequency modulator are said oscilla- tor signals. This feature covers a phase-locked loop cir- cuit for which said frequency modulator receives said os- cillator signals and provides said frequency modulated sig- nals on the basis of said oscillator signals at the output.

In a further feature, said frequency modulator is a di- vider. Said controller may control a divider ratio of said divider for said frequency adjustment. Said divider ratio may be changed in given steps. When said phase detector is in the linear range again, said divider ratio may be changed in said given steps in order to reach said desired frequency. Alternatively, said divider ratio suitable for generating frequency modulated signals with said desired frequency may be applied when said phase detector is in said linear range again.

In an alternative feature, said frequency modulator is a multiplier. Said controller may control a multiplier ratio of said multiplier for said frequency adjustment. Said mul- tiplier ratio may be changed in given steps. When said phase detector is in the linear range again, said multi- plier ratio may be changed in said given steps in order to reach said desired frequency. Alternatively, said multi- plier ratio suitable for generating frequency modulated signals with said desired frequency may be applied when said phase detector is in said linear range again.

In another feature of the invention, said phase-locked loop comprises a charge pump providing charge pump signals on the basis of said phase difference signals as input signals applied to said voltage controlled oscillator.

In a further feature, said phase-locked loop comprises a loop filter filtering said input signals applied to said voltage controlled oscillator.

In yet a further feature, said phase detector is an EXOR gate.

In another feature, said linear range detector is an inte- gral part of said phase detector.

In a second aspect, a controller for a phase-locked loop circuit with a voltage controlled oscillator generating os- cillator signals with frequencies dependent on input sig- nals applied to said voltage controlled oscillator ; a fre- quency modulator receiving input signals and generating frequency modulated signals; a phase detector providing phase difference signals on the basis of the phase differ- ence between said frequency modulated signals and further signals; a linear range detector detecting whether said phase detector is in a linear range by analysis of said frequency modulated signals and said further signals and generating linear range signals; is characterised in that said controller receiving said linear range signals con- trols the frequency of said frequency modulated signals by a frequency adjustment so that said phase detector gets back into said linear range after a change in the frequency of said frequency modulated signals to a desired frequency.

In a third aspect of the invention, a method for control- ling a frequency modulator receiving input signals and gen- erating frequency modulated signals in a phase-locked loop circuit with a voltage controlled oscillator generating os- cillator signals with frequencies dependent on input sig- nals applied to said voltage controlled oscillator ; a phase detector providing phase difference signals on the basis of the phase difference between said frequency modulated sig- nals and further signals ; a linear range detector detecting whether said phase detector is in a linear range by analy- sis of said frequency modulated signals and said further signals; is characterised by the following steps: Genera- tion of linear range signals by the linear range detector; Reception of said linear range signals by a controller ; Ad- justment of the frequency of said frequency modulated sig- nals by the controller so that said phase detector gets back into said linear range after a change in the frequency of said frequency modulated signals to a desired frequency.

Embodiments of the invention will now be described, by the way of example only, with reference to the following draw- ings in which: Fig. 1 is a block diagram of a PLL circuit ; Fig. 2 is a circuit diagram showing the EXOR phase detector including the linear range detector used in the circuit of figure 1 ; FIG. 3 is a timing diagram for the EXOR phase detector and the linear range detector for a frequency increase ; FIG. 4 is a timing diagram for the EXOR phase detector and the linear range detector for a frequency decrease.

Referring to fig. 1, a block diagram of a PLL circuit is shown. The PLL comprises the phase detector PD including a linear range detector LRD, the charge pump CP, the loop

filter LF, the voltage controlled oscillator VCO, the di- vider DIV and the divider ratio control DRC.

The phase detector PD including the linear range detector LRD receives the reference signals UREF and the signals uDlv provided by the divider DIV. Besides it has a further input for the frequency direction signal UFD indicating whether the divider ratio increased or decreased during the last change of the divider ratio.

The phase detector PD generates the phase difference sig- nals UPD. The digital signal UPD is converted to an analog signal ucp in the charge pump CP suitable for the control of the VCO.

Before the signal generated by the charge pump uCp is re- ceived at the voltage controlled oscillator, the signal ucp is filtered in the loop filter LF which outputs the loop filter signal ULF which controls the VCO. The VCO generates the signal uvco whose frequency depends on the input signal ULF- The uvco signal is used by an application A and delivered to the divider DIV. The divider DIV is connected to the phase detector via two signals lines from where the divider DIV receives two control signals Ucono and Uconi. The divider ra- tio control circuit comprises a further input for division ratio signal URA with several bits and an output for the divider ratio control signal uDRC received at the input of the divider DIV.

Referring to Fig. 2, a circuit diagram of the EXOR phase detector and the linear range detector used in the circuit of figure 1 is shown. The UREF signals and UD signals and the inverted UFD signals are received at

the inputs of a circuit block comprising six NAND gates 21 to 26 and realising two functions F25 and F26.

The signal provided by the NAND gate 25 corresponds to the function F25 given by: F25 (uDIV # uFD) + (uREF # u'FD) The signal provided by the NAND gate 26 corresponds to the function F26 given by: F26 = (uREF # uFD) + (UDIV U u'FD) Hence, the F25 = uDlv and F26 = UREF for UFD = 1 and the F25 = UREF and F26 = uDIV for UFD = 0.

The outputs of the NAND gates 25 and 26 are connected to the trigger inputs of the toggle flip-flops TF1 and TF2. Therefore, the flip-flops TF1 and TF2 toggle with half the frequency of the signals Ups ? and uDIV and a duty factor of 50 % which is most suitable for EXOR phase detectors. The signals uTF1 and uTF2 at the output of the toggle flip-flops TF1 and TF2 respectively are not shifted with respect to the corresponding signals with twice their frequencies. The signals uTF1 and uTF2 are analysed in the EXOR gate phase detector EXOR1 which provides the phase difference signals UPD at its output. The commutation of the UTF1 signals and uTF2 signals for different values of the frequency direc- tion signals UFD does not influence the operation of the gate EXOR1.

The D flip-flop DF operates as linear range detector. For UFD = 1, the flip-flop DF is triggered by the signals uTF1 = u REFhalf (the inverse of the signals with half the frequency

of the UREF signals), and the signals uTF2=u'DIvhalf (the in- verse of the signal with half the frequency of the uDIV sig- nals) are fed to the input of the flip-flop DF whereas, for uFD = 0, the flip-flop DF is triggered by the signals u'DIvhalf and the signals u'REFhalf are fed to the input of the flip-flop DF. The flip-flop DF outputs the signals ut rig# For uFD = 1, Utrig corresponds to the value of u'DIvhalf at its D input during the last rise of u'REFhalf from 0 to 1. In case that utrig=1, u'DIvhalf is ahead of u'REFhalf, i. e. UDIVhalf is ahead of UREFhalf, and vice versa in case that utriggered=0.

For uFD = 0, utrig corresponds to the value of u'REFhalf at its D input during the last rise of UDIVhalf from 0 to 1. In case that Utrig =1, u'REFhalf is ahead of u'DIVhalf, i. e. UREF is ahead of uDIV, and vice versa in case that utrig=0. Hence, the value of utrig indicates which one of the two signals uDIV or UREF is ahead. A change in Utrig indicates that the order of uDIV or UREF has changed.

The values of utrig and UFD are entered in the negated EXOR gate EXOR2 corresponding to the function ucono : (u'trif u'FD) + (utrig # uFD) The signal Ucono cannot solely indicate whether the PLL cir- cuit is in the linear range or not. However, if we ensure that ucon0 = 0 in steady-state conditions by means of the divider ratio control DRC, ucono = 1 automatically signifies that the PLL circuit has left the linear range. In steady- state conditions, UREF is therefore always ahead of UDIV. As the order of UREF and uDIV does not matter, this does not re- sult in any limitations. When the sign of UFD changes also the signal corresponding to utrig changes. The commutation of the signals UREF and uDIV by the gates 21 to 26 ensures that UREF and uDIv maintain their relative positions. Other- wise, the relative order of UREF and uDIV would change for different UFD values requiring a cycle slip.

The output of the AND gate 27 is used for the control of the direction in which the divider ratio is changed by a given number. The output of the AND gate 27 is given by the function Uconi : ucon1 = ucon0 # uFD The signal acon, depends on the frequency direction and can be used to indicate the direction of an divider ratio ad- justment ADIV-If the linear range has been left, the value of Uconi indicates whether the divider ratio should be de- creased or increased by a certain amount ADIV in order to bring the phase detector back into the linear range. Only three combinations for ucon0 and ucon1 can occur. Their sig- nification is given in the following table: Ucon0 Uconl ADIV 0 0 0 0 1 +1 1 1-1 The frequency adjustment can be repeated several times depending on the values of Ucono and uconl until the phase detector circuit is in the linear range. When the phase detector is in the linear range, the fre- quency can be changed by an amount ADIV in order to ar- rive at the desired divider ratio. Alternatively, the desired divider ratio may be applied after a certain hold time.

FIG. 3 shows a timing diagram for the output signals of the toggle flip-flops TF1 and TF2, the D flip-flop DF and the phase detector EXOR1 for an increase of the frequency (the signal indicating the frequency change is set to a high

state). When the phase error between the signals provided by the toggle flip-flops TF1 and TF2 accumulates to more than +90 degrees, the D flip-flop rises to a high state in- dicating the crossing of the linear range border.

The output signals of the D flip-flop DF and the frequency direction signals are encoded with the help of the negated EXOR2 gate and AND gate 27 and transferred to the divider ratio control. The division ratio is reduced at two in- stances in order to bring the PLL circuit back into the linear range. This procedure repeats until the phase detec- tor is in the linear range.

FIG. 4 shows a timing diagram for the output signals of the toggle flip-flops TF1 and TF2, the D flip-flop DF and the phase detector EXOR1 for a decrease of the frequency (the signal indicating the frequency change is set to a low state). When the phase error between the signals outputted by the toggle flip-flops TF1 and TF2 accumulates to more than-90 degrees, the D flip-flop rises to a high state in- dicating the crossing of the linear range border.

The output signals of the D flip-flop DF and the frequency direction signals are encoded with the help of the negated EXOR2 gate and AND gate 27 and transferred to the divider ratio control. The division ratio is reduced at two in- stances in order to bring the PLL circuit back into the linear range. This procedure repeats until the phase detec- tor is in the linear range.