Title:
PLL CIRCUIT DEVICE AND CONTROL DEVICE
Document Type and Number:
WIPO Patent Application WO/2008/123542
Kind Code:
A1
Abstract:
Provided are a PLL circuit and a control device in which a jitter is reduced. The
PLL circuit (10A) outputs an oscillation clock (32) obtained by multiplying
a reference clock (24) and corrects the oscillation clock (32) by using a first
correction signal (28) based on a phase difference between the reference clock
(24) and an oscillation clock (32). Furthermore, the PLL circuit (10A) includes:
a signal generation unit (12) which generates a first waveform signal (36) synchronized
with the reference clock (24); a sampling unit (14) which samples a first waveform
signal (36) by using a higher frequency than the reference signal (24) so as to
obtain a first sample value (26); a comparison unit (16) which compares the first
sample value (26) to a second sample value (34) obtained by sampling a second waveform
signal (38) based on a waveform when the PLL circuit (10A) is in a stable state and
outputs a first correction signal based on a difference between them; and an output
unit (20) which outputs the oscillation clock (32) adjusted according to the
second correction signal (correction signal).
Inventors:
KONDOH HITOSHI (JP)
KOBAYASHI FUMINORI (JP)
INOUE MANABU (JP)
KOBAYASHI FUMINORI (JP)
INOUE MANABU (JP)
Application Number:
PCT/JP2008/056538
Publication Date:
October 16, 2008
Filing Date:
March 26, 2008
Export Citation:
Assignee:
SYSTEM LSI CO LTD (JP)
KYUSHU INST TECHNOLOGY (JP)
KONDOH HITOSHI (JP)
KOBAYASHI FUMINORI (JP)
INOUE MANABU (JP)
KYUSHU INST TECHNOLOGY (JP)
KONDOH HITOSHI (JP)
KOBAYASHI FUMINORI (JP)
INOUE MANABU (JP)
International Classes:
H03L7/085; H03L7/08
Foreign References:
| JPH05207417A | 1993-08-13 | |||
| JPS6424631A | 1989-01-26 | |||
| JPH03186017A | 1991-08-14 |
Attorney, Agent or Firm:
OKADA, Kei (Hosoya-cho Ota-city, Gunma 42, JP)
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