VARIATIONS

TECHNICAL FIELD

The disclosure relates, in general, to a power amplifier and method of controlling a power amplifier, and more particularly, although not exclusively, to a power amplifier and method of controlling a power amplifier to distribute a peak amplifier signal to compensate for load variations, enabling minimization or elimination of some or all load modulation of the main and peak amplifier. A power amplifier may be driven by a drive circuit to perform the method. The power amplifier or method may be used in a mobile communications base station.

BACKGROUND

Power amplifiers may need to operate with signals that comprise high peak to average power ratios. For such signals, a power amplifier will operate at some back off power (that is, below maximum power), but will need to be able to deal with peaks of power which will occur sporadically. This makes it difficult to design an amplifier that is power efficient. Due to high peak to average ratios in mobile telecom standards signals, i.e. for LTE, close to 9dB, the amplifier size should be eight times bigger than the power that the PA will, on average, deliver to the antenna load. This makes it difficult to implement a high efficiency, low power consumption, power amplifier (PA).

Both the known so-called Chireix and Doherty amplifiers share a common methodology in the form of dynamic load modulation, which enables different components of the amplifier (i.e. transistors) to operate at maximum voltage swing and therefore be power efficient when they are driven with some back off.

A Doherty amplifier uses a main amplifier and a peak (or auxiliary) amplifier. The main amplifier is an amplifier which operates all the time there is some signal at the input of the amplifier. The peak (or auxiliary) amplifier is an amplifier which operates when the input signal exceeds a certain predefined power threshold value. Below this threshold value, the peak amplifier is idle.

US2005/0134377 describes an implementation of a Doherty power amplifier. The main amplifier is implemented as a balanced amplifier and an auxiliary amplifier is connected to the isolated port of a quadrature hybrid combiner. The total power is added and collected at the output of the quadrature hybrid.

SUMMARY

In a first aspect there is provided a power amplifier comprising a hybrid combiner comprising a first input port and a second input port, an isolated port and an output port, wherein the hybrid combiner is configured deliver an output power at the output port; a balanced amplifier arrangement comprising a main amplifier arrangement and first and second peak amplifiers, wherein outputs of the main amplifier arrangement and outputs of the first and second peak amplifiers are coupled with the first and second input ports of the hybrid combiner so as to provide output power at the output port; a third peak amplifier having an output coupled to the isolated port of the hybrid combiner; a peak signal distribution circuit configured to provide a peak amplification signal to the input ports of the first, second and third peak amplifiers. The hybrid combiner (sometimes referred to in the art as a hybrid coupler) may be a quadrature hybrid combiner.

Providing the peak amplification signal at a peak amplifier coupled to the isolated port (i.e. a usually terminated output port) of the hybrid combiner, and also at first and second peak amplifiers coupled to input ports of the hybrid combiner, allows for a low load-pull ratio and mitigation of the off impedance seen by the main amplifier arrangement. Thus, load modulation at the amplifiers may be controlled so as to reduce or even eliminate the LPR over the whole power range. As a result, it is possible to increase the back off average efficiency of the power amplifier at high power (e.g. 1KW operating at 9dB Back off) wide band (i.e. 40% Bandwidth) power amplifier designs. In other words, a power amplifier architecture capable of operating at high efficiency at a useful back off level is provided which is also operable at high efficiency over a wide bandwidth. Such power amplifiers are used in modern mobile telecommunication infrastructures such as in LTE or 5G networks.

In a first implementation of the first aspect, the peak signal distribution circuit comprises a first peak hybrid splitter configured to receive the peak amplification signal at an input port and deliver the peak amplification signal at respective first and second output ports, a second hybrid splitter comprising an input port and first and second output ports coupled to inputs of the first and second peak amplifiers, wherein the first output port of the first hybrid splitter is coupled to the input of the third peak amplifier and the second output port of the first hybrid splitter is coupled to the input of the second hybrid splitter. The first peak hybrid splitter may comprise a 180 degree hybrid splitter configured to provide a 180 degree shifted signal at the first output port and a direct (in-phase) signal at the second output. The second peak hybrid splitter may comprise a quadrature hybrid splitter configured to provide a quadrature shifted signal at the first output port and a direct (in-phase) signal at the second output port. Thus, the peak signal can be conveniently provided in quadrature at the first and second amplifiers which permits their combination at the hybrid combiner, while at the same time providing the peak signal directly to the third peak amplifier to provide power at the isolated port of the hybrid combiner to modulate the impedance presented at the inputs of the hybrid combiner.

In a second implementation of the first aspect, the output of the first peak amplifier is coupled to the first input port of the hybrid combiner and the output of the second peak amplifier is coupled to the second input port of the hybrid combiner such that the first and second peak amplifiers are configured as a balanced amplifier. In other words, the first and second peak amplifier are arranged as limbs of a balanced amplifier which together with the third peak amplifier helps to reduce the load pull ratio of the main amplifier arrangement.

In a third implementation of the first aspect, the main amplifier arrangement comprises a first main amplifier and a second main amplifier, wherein the output of the first main amplifier is coupled to the first input port of the hybrid combiner and the output of the second main amplifier is coupled to the second input port of the hybrid combiner such that the first and second main amplifiers are configured as a balanced amplifier. Thus, the main amplifier arrangement is arranged as elements of a balanced amplifier together with the first and second peak amplifiers (peak amplifier arrangement). Thus, the signals from the balanced amplifier of the main amplifier arrangement may be combined with those of the balanced amplifier of the peak amplifier arrangement (which operates simultaneously with the third peak amplifier) thereby providing high efficiency at back off and reduces load pull ratio of the balanced main amplifier arrangement.

In a fourth implementation of the first aspect, the power amplifier further includes a third hybrid splitter configured to receive a main input signal at an input port and deliver a first main output signal and a second main output signal at respective first and second output ports, the first and second output ports of the third hybrid splitter are coupled to respective inputs of first and second main amplifiers, and the outputs of the first and second main amplifiers are coupled to the first and second input ports of the hybrid combiner via respective first and second impedance modifying elements. The third hybrid splitter may comprise a quadrature hybrid splitter arranged to provide a quadrature output at the first output and a direct (in- phase) signal at the second output. Thus, the outputs of the first and second peak amplifiers may be matched with the outputs of the first and second main amplifiers to permit effective combination of the respective main and peak amplified signals at the hybrid combiner. For example, the impedance modifying element may be a matching network, a transmission line (e.g. a quarter wavelength transmission line) or any other arrangement which enables the signals to be effectively coupled at the inputs to the hybrid combiner.

In a fifth implementation of the first aspect, the power amplifier is configured to provide power from the main amplifier arrangement and increase the main amplifier arrangement output power to a predetermined power level, upon reaching the predetermined power level, provide power from the first, second and third peak amplifiers and increase the output power level provided by the first, second and third peak amplifiers while continuing to provide the output power at the main amplifier at the predetermined level, and increase the output power level at the first, second and third peak amplifiers until a predetermined output power level is provided at the output port of the power amplifier circuit. This sequential driving methodology allows a low or optimal load pull ratio to be obtained even without turning off the main amplifier (as used in the prior art). Thus, across the full power range it is possible to control the relative amplitude and phase of the main and peak signals provided to the main and peak amplifiers, thereby achieving the benefits from tracking the impedances over a wide frequency range.

In a sixth implementation of the first aspect, at least one of the first and second main amplifiers comprises a power amplifier arrangement with extended high efficiency towards a non-zero back off level. In an eighth implementation of the first aspect, the power amplifier arrangement may be any one of: a Doherty power amplifier, an N-way Doherty power amplifier, a Chireix amplifier and an Envelope Tracking amplifier. Thus, the back off efficiency of the power amplifier may be further increased with a low load-pull ratio across the power range.

In a second aspect, there is provided a method for controlling a power amplifier, said power amplifier comprising: a main amplifier arrangement and a balanced amplifier arrangement having peak amplifiers which are connected using a hybrid combiner, wherein power is delivered at an output port of the hybrid combiner, the method comprising: providing power from the main amplifier arrangement and increasing the output power provided by the main amplifier arrangement to a predetermined power level, upon reaching the predetermined power level, providing power from the peak amplifiers and increasing the power level provided by the peak amplifiers while continuing to supply output power via the main amplifier; and continuing to increase the power level provided by the peak amplifiers until a predetermined output power level is provided by the power amplifier.

In a first implementation of the second aspect, power is provided from the main amplifier arrangement by obtaining power from a main amplifier connected to an isolated port of the hybrid combiner. This sequential driving allows the impedance presented to the peak amplifiers to be controlled e.g. by controlling the amplitude and phase relationships between the main and peak amplifiers. Further, the load pull ratio of the main amplifier will be kept to a low or minimum value.

The peak amplifiers may comprise first and second peak amplifiers corresponding to respective branches of the balanced amplifier. The power size of the peak amplifiers may be balanced with the back off and size of the main amplifier to provide a desired back off of the entire power amplifier. For example, peak amplifiers having a smaller power size can be used to reduce the off-impedance problems. This will reduce the back off of the power amplifier as a whole but this can be compensated if a main amplifier arrangement (e.g. an N-way Doherty) with more back off is chosen.

In a second implementation of the second aspect, power is provided from a main power amplifier arrangement comprising a power amplifier with extended high efficiency towards a non-zero back off level. By using a power amplifier with an extended back off as part of the main amplifier arrangement, the back off provided when applying the sequential driving to the power amplifier may be extended further. Further, as mentioned above this allows smaller peak amplifiers to be used to reduce the problems associated with off-impedance, where any reduction in back off caused by using smaller peak amplifiers is compensated by the extended high efficiency at back off of the main amplifier arrangement. In a third implementation of the second aspect, the main amplifier arrangement comprises any of a single-ended amplifier, a Doherty amplifier, a Chireix amplifier, an N-way Doherty amplifier, and an envelope tracking amplifier. Any of these alternatives may be used to extend the back off while maintaining high efficiency.

In a fourth implementation of the second aspect, the power amplifier further comprises a third peak amplifier coupled to an isolated port of the hybrid combiner, wherein the main amplifier arrangement and the peak amplifiers of the balanced amplifier are coupled to first and second input ports of the hybrid combiner so as to provide power at the output port, and the method further comprises upon reaching the predetermined power level, providing power from the third peak amplifier together with the peak amplifiers of the balanced amplifier, and increasing the power level provided by the third peak amplifier.

This reduces off-impedance losses in the power amplifier, that are introduced by the third peak amplifier, and impedance control is achieved over the whole power range. Accordingly, it is possible to increase the back off average efficiency in high power (e.g. 1KW operating at 9dB back off) wide band (e.g. 40% bandwidth) power amplifier designs. Such power amplifier topologies may be used in modern mobile communications (LTE, 4G, etc.) networks e.g. in a base station.

In a fifth implementation of the second aspect, the main amplifier arrangement comprises a first main amplifier and a second main amplifier, wherein the output of the first main amplifier is coupled to the first input port of the hybrid combiner and the second main amplifier is coupled to the second input port of the hybrid combiner such that the first and second main amplifiers are configured as a balanced amplifier, and providing power to the main amplifier arrangement comprises providing power to the first and second amplifiers. Thus, the main amplifier arrangement is arranged as elements of a balanced amplifier together with the first and second peak amplifiers (peak amplifier arrangement) The signals from the balanced amplifier of the main amplifier arrangement may be combined with those of the balanced amplifier of the peak amplifier arrangement (which operates simultaneously with the third peak amplifier) thereby providing high efficiency at back off and reduces load pull ratio of the balanced main amplifier arrangement. In a sixth implementation of the second aspect, the main amplifier arrangement comprises a pair of first and second Doherty amplifiers respectively coupled to the first and second input ports of the hybrid combiner, and providing power from the main amplifier arrangement comprises providing power from a main amplifier of the respective first and second Doherty amplifiers and increasing the output power supplied, and upon reaching a predetermined power level of the main amplifier of the first and second Doherty amplifiers, providing power from a peak amplifier of the first Doherty amplifier and a peak amplifier of the second Doherty amplifier. This allows back off to be further extended while maintaining high efficiency. In other words, the first and second Doherty amplifiers will work as a main amplifier arrangement coupled to the hybrid coupler input ports and provide power until a predetermined power level is reached. The total amplifier back off will be extended by the back off of the Doherty amplifiers used for the main amplifier arrangement.

In other implementations of the second aspect, the main amplifier arrangement may comprise a pair of power amplifiers with extended high efficiency towards a non-zero back off level, for example, any of a single-ended amplifier, a Doherty amplifier, a Chireix amplifier, an N- way Doherty amplifier, and an envelope tracking amplifier. Providing power to the main amplifier arrangement comprises providing power to the power amplifiers. Any of these alternatives may be used to extend the back off while maintaining high efficiency.

In a third aspect, there is provided a power amplifier comprising a hybrid combiner having an output port at which power is delivered; a main amplifier arrangement connected to an isolated port of the hybrid combiner; a balanced amplifier arrangement having first and second peak amplifiers, which are connected using the hybrid combiner, and wherein the power amplifier is configured to perform the method according to any of the first to third implementations of the second aspect.

In a fourth aspect, there is provided a drive circuit for driving a power amplifier, the drive circuit comprising a base band digital signal processing unit comprising a look up table/digital pre-distorter unit, first and second digital-to-analog converters, up-converters, and an RF module, wherein look up table/digital pre-distorter unit is configured to provide respective first and second digital outputs to the first and second digital-to-analog converters, and wherein the first and second digital-to-analog converters are configured to provide respective outputs to the up-converters, the up-converters configured to provide a main drive signal and a peak drive signal at their outputs for supply to first and second channels of the power amplifier.

The driver circuit may comprise a signal processing unit for receiving a modulated input signal and generating main drive signals and peak drive signals as outputs, The output signals may be generated so as to cause a Doherty power amplifier topology having multiple input (main and peak inputs) signal outputs to perform the control steps of any method described in aspects and implementations herein.

In a first implementation of the fourth aspect, the drive circuit is configured to provide power from the main amplifier arrangement by providing power to a main amplifier connected to an isolated port of the hybrid combiner. This sequential driving allows the impedance of the peak amplifiers to be controlled while keeping the load pull ratio of the main amplifier arrangement to a low or minimum value.

The peak amplifiers may comprise first and second peak amplifiers corresponding to respective branches of the balanced amplifier. The power size of the peak amplifiers may be balanced with the back off and size of the main amplifier to provide a desired back off of the entire power amplifier. For example, peak amplifiers having a smaller power size can be used to reduce the off-impedance problems. This will reduce the back off of the power amplifier as a whole but this can be compensated if a main amplifier arrangement (e.g. an N-way Doherty) with more back off is chosen.

In a second implementation of the fourth aspect, the drive circuit is configured to provide power from a main power amplifier arrangement comprising a power amplifier with extended high efficiency towards a non-zero back off level. By using a power amplifier with an extended back off as part of the main amplifier arrangement, the back off provided when applying the sequential driving to the power amplifier may be extended further. Further, as mentioned above this allows smaller peak amplifiers to be used to reduce the problems associated with off-impedance, where the reduction in back off caused by using smaller peak amplifiers is compensated by the extended high efficiency at back off of the main amplifier arrangement. In a third implementation of the fourth aspect, the main amplifier arrangement driven by the drive circuit may comprise any of a single-ended amplifier, a Doherty amplifier, a Chireix amplifier, an N-way Doherty amplifier, and an envelope tracking amplifier. Any of these alternatives may be used to extend the back off while maintaining high efficiency.

In a fourth implementation of the fourth aspect, the power amplifier further comprises a third peak amplifier coupled to an isolated port of the hybrid combiner, wherein the main amplifier arrangement and the peak amplifiers of the balanced amplifier are coupled to first and second input ports of the hybrid combiner so as to provide power at the output port, and the drive circuit further configured to upon reaching the predetermined power level, provide power from the third peak amplifier together with the peak amplifiers of the balanced amplifier, and increase the power level provided by the third peak amplifier.

This reduces off impedance losses in the power amplifier and impedance control is achieved over the whole power range. Accordingly, it is possible to increase the back off average efficiency in high power (e.g. 1KW operating at 9dB back off) wide band (e.g. 40% bandwidth) power amplifier designs. Such power amplifier topologies may be used in modern mobile communications (LTE, 4G, etc.) networks e.g. in a base station.

In a fifth implementation of the fourth aspect, the main amplifier arrangement comprises a first main amplifier and a second main amplifier, wherein the output of the first main amplifier is coupled to the first input port of the hybrid combiner and the output of the second main amplifier is coupled to the second input port of the hybrid combiner such that the first and second main amplifiers are configured as a balanced amplifier, and the drive circuit is configured to provide power to the main amplifier arrangement by providing power to the first and second amplifiers. Thus, the main amplifier arrangement is arranged as elements of a balanced amplifier together with the first and second peak amplifiers (peak amplifier arrangement) and the signals from the balanced amplifier of the main amplifier arrangement may be combined with those of the balanced amplifier of the peak amplifier arrangement at the hybrid combiner thereby providing low load pull across the power range and a reduction in off impedance losses.

In a sixth implementation of the fourth aspect, the main amplifier arrangement comprises a pair of first and second Doherty amplifiers respectively coupled to the first and second input ports of the hybrid combiner, and the drive circuit is configured to provide power from the main amplifier arrangement by providing power from a main amplifier of the respective first and second Doherty amplifiers and increasing the output power supplied, and upon reaching a predetermined power level of the main amplifier of the first and second Doherty amplifiers, providing power from a peak amplifier of the first Doherty amplifier and a peak amplifier of the second Doherty amplifier. This allows back off to be further extended while maintaining high efficiency. In other words, the first and second Doherty amplifiers will work as a main amplifier arrangement coupled to the hybrid coupler input ports and provide power until a predetermined power level is reached. The total amplifier back off will be extended by the back off of the Doherty amplifiers used for the main amplifier arrangement.

In other implementations of the fourth aspect, the main amplifier arrangement may comprise a pair of power amplifiers with extended high efficiency towards a non-zero back off level, for example, any of a single-ended amplifier, a Doherty amplifier, a Chireix amplifier, an N-way Doherty amplifier, and an envelope tracking amplifier. The drive circuit may be configured to provide power to the main amplifier arrangement by providing power to the power amplifiers. Any of these alternatives may be used to extend the back off while maintaining high efficiency.

In a further aspect, there is provided a base station for a communications network, the base station comprising the power amplifier according to any of the aspects and implementations recited herein.

In a yet further aspect, there is provided a computer program comprising computer executable instructions which upon execution cause drive circuitry to control a power amplifier according to any implementation of the second aspect. The computer program may be embodied on a computer readable carrier medium and comprise instructions which when executed by one or more processors cause the method of any implementation of the second aspect to be performed. The carrier medium may be transitory or non-transitory.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which: Figure 1 A shows a schematic diagram of a Doherty power amplifier circuit according to the prior art;

Figure IB shows a block diagram of a Doherty power amplifier circuit according to the prior art;

Figure 2 shows is diagram illustrating a trade-off between efficiency an output power;

Figure 3 illustrates a distributed balanced Doherty power amplifier according to an example;

Figure 4 illustrates a method of controlling a power amplifier according to an example;

Figure 5 is a plot illustrating driving currents for a distributed balanced Doherty power amplifier according to an example;

Figure 6 is a plot illustrating phases of driving current signals in a distributed balanced Doherty power amplifier according to an example;

Figure 7 illustrates a distributed balanced Doherty power amplifier according to an example;

Figure 8 illustrates a distributed balanced Doherty power amplifier with a main amplifier implemented as a Doherty amplifier according to an example;

Figure 9 illustrates a plot of driving currents of a distributed balanced Doherty power amplifier with a main amplifier implemented as a Doherty amplifier according to an example;

Figure 10 illustrates a plot of phases of driving currents of a distributed balanced Doherty power amplifier with a main amplifier implemented as a Doherty amplifier according to an example;

Figure 11 illustrates a plot of impedances of a distributed balanced Doherty power amplifier with a main amplifier implemented as a Doherty amplifier according to an example; Figure 12 illustrates a plot of theoretical efficiency against power for a distributed balanced Doherty power amplifier with a main amplifier implemented as a Doherty amplifier according to an example;

Figure 13 illustrates a balanced single ended single ended (BSS) power amplifier according to an example;

Figure 14 illustrates a plot of driving currents for a BSS power amplifier according to an example;

Figure 15 illustrates a balanced single ended Doherty (BSD) amplifier with a main amplifier implemented as a Doherty amplifier;

Figure 16 illustrates a BSD amplifier with a main amplifier implemented as an N-way Doherty amplifier; and

Figure 17 illustrates a controller comprising a driving circuit according to an example.

DESCRIPTION

Embodiments of the disclosure are described below in sufficient detail to enable those of ordinary skill in the art to embody and implement the systems and processes herein described. It is important to understand that embodiments can be provided in many alternate forms and should not be construed as limited to the examples set forth herein.

Accordingly, while embodiments can be modified in various ways and take on various alternative forms, embodiments thereof are shown in the drawings and described in detail below as examples. There is no intent to limit to the particular forms disclosed. On the contrary, all modifications, equivalents, and alternatives falling within the scope of the appended claims should be included. Elements of the example embodiments are consistently denoted by the same reference numerals throughout the drawings and detailed description where appropriate.

The terminology used herein to describe embodiments is not intended to limit the scope. The articles “a,” “an,” and “the” are singular in that they have a single referent, however the use of the singular form in the disclosure should not preclude the presence of more than one referent. In other words, elements referred to in the singular can number one or more, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including,” when used herein, specify the presence of stated features, items, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, items, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein are to be interpreted as is customary in the art. It will be further understood that terms in common usage should also be interpreted as is customary in the relevant art and not in an idealized or overly formal sense unless expressly so defined herein.

Practical radio frequency (RF) devices have a limited output power range where the drain efficiency can be kept elevated. An example of such a limited output power range for a typical prior art device is illustrated in figure 2 for example. Because such a power amplifier (PA) uses a load modulation technique, this change in power is achieved by actively load pulling the load. The best PA architecture will be the one that achieves high efficiency back off (BO) with a small load pull ratio (LPR) because the available LPR at which high efficiency can be obtained is limited.

Smaller LPR has another benefit which is the RF bandwidth (BW). Smaller LPR will make possible to implement broadband matching networks, capable of tracking the loads for the different states of the amplifiers which constitute the PA architecture.

Another important issue to consider is what occurs when switching on/off different power amplifiers. This is typically done in Doherty type architectures where peak PA’s are off until a certain threshold power is crossed. This extends the BO of the efficiency without incrementing the LPR. The absence of peak amplifiers is the reason why, for example,

Chireix amplifiers have higher LPRs than Doherty amplifiers. Switching of peak amplifiers introduces another issue, which relates to the off impedance of the amplifiers (transistors) when they are switched off (i.e. not providing power). Ideally, an open circuit is provided when the peak amplifier is off, but in practice it is difficult to achieve a good (high reflective) load over a wide frequency range. Connecting the peak amplifiers in the balanced side will make the PA reduce the load pull ratio. However, it is then sensitive to the off impedance of the peak amplifiers. Connecting the peak amplifiers in the isolated port will solve the off-impedance issue, but uses a very high load pull ratio to achieve an acceptable back off level e.g. 5:1 to obtain 9.54dB.

According to embodiments, there is provided a topology to distribute a peak amplifier signal to compensate for load variations, enabling minimization or elimination of some or all load modulation of the main and peak amplifier. Further, according to embodiments, a sequential driving methodology is used to take advantage of the LMBA impedance tracking over frequency.

A circuit according to a first embodiment is shown in Figure 3 which will be referred to as a distributed Balanced Doherty power amplifier (dBD PA).

A power amplifier arrangement 300 is shown that includes a quadrature hybrid coupler 310 (configured as a hybrid combiner) and a balanced amplifier arrangement 320 having outputs of its in-phase and quadrature branches coupled to input ports 310a, 310b of the hybrid coupler 310 such that the signals are combined and provided at an output port 310c to an output load 360. A peak distribution circuit 340 receives a peak driving signal (e.g. from a driving circuit) and distributes (provides) the peak signal to first and second (single ended) peak amplifiers 322-1, 322-2 at respective branches of a balanced amplifier arrangement 320 and to a third (single ended) peak amplifier 330 that has its output 330b connected to an isolated port 310d of the hybrid coupler 310. First and second main amplifiers 321-1,321-2 are arranged to receive a main driving signal at their inputs 321-la, 321-2a and are coupled to respective input ports 310a, 310b of the hybrid coupler 310 via impedance modifying elements 323 a and 323b respectively to match their signal output with that of the first and second peak amplifiers 322-1, 322-2. The impedance modifying elements may comprise (but are not limited to) transmission lines having some electrical length or other types of matching elements or network that matches the signal outputs of the main 321-1, 321-2 and peak amplifiers 322-1, 322-2, for example.

The peak distribution circuit 340 includes a hybrid 180-degree coupler configured as a first hybrid splitter 341, which is arranged to receive a peak input signal at an input port 341d and provide a direct signal at output port 341c and a 180-degree shifted signal at output port 341b. An isolated port 341a of the first hybrid splitter 341 is terminated with a predetermined load Zo (e.g. a resistor with a fixed impedance). The input 330a of the third peak amplifier 330 is connected to the output port 341b such that the 180-degree shifted peak input signal is fed to the third peak amplifier 330 via the first hybrid splitter 341 and power is provided from the third peak amplifier to the isolated port 3 lOd of the hybrid coupler 310.

The direct output 341c of the first hybrid splitter 341 is coupled to an input 342a of a second hybrid splitter 342. In this embodiment, the second hybrid splitter 342 is a hybrid quadrature coupler configured as a quadrature splitter. A direct output port 342b of the second hybrid splitter is connected to the input 322-2a of the second peak amplifier 322. A quadrature output port 342c is connected to the input 322- la of the first peak amplifier 322-1. The isolated port 342d is terminated with a fixed impedance Zo. Accordingly, the first and second peak amplifiers 322-1, 322-2 are effectively configured as a peak balanced amplifier arrangement providing quadrature and in-phase signals at respective inputs 310a, 310b of the hybrid combiner 310.

A further hybrid quadrature coupler 350 is configured as a third hybrid signal splitter for receiving the main drive signal and delivering direct and quadrature main drive signals to the first and second main amplifiers 321-1, 321-2 respectively such that the first and second main amplifiers are configured as a main balanced amplifier. The main driving signal is provided to an input port 350a of the third hybrid splitter 350 and direct and quadrature signals provided at output ports 350b and 350c respectively. The direct output port 350b is connected to the input 321-la of the first main amplifier 321-1. The quadrature output port 350c is connected to the input 321 -2a of the second main amplifier 321-2. The port 350d is an isolated port terminated with a fixed impedance Zo.

Accordingly, a multiple input single output (MISO) power amplifier architecture is provided with 2 channels (main drive signal and peak drive signal) implementing a Doherty power amplifier architecture. Thus, according to the embodiment shown in Figure 3, the peak drive signal is distributed to power amplifiers connected both at the isolated port of the hybrid coupler and to the other input ports of the hybrid coupler as balanced amplifier. This distribution of the peak can be used to neutralize the load pull ratio of the main amplifier, solving the load pull ratio issue. Accordingly, the first peak amplifier 322-1 and the second peak amplifier 322-2 introduce a load pull over the main amplifier arrangement e.g. first and second main amplifiers 321-1,

321-2. The third peak amplifier 330 which is connected to the isolated port 3 lOd cancels the load pull of the first peak amplifier 322-1 and the second peak amplifier 322-2 thereby achieving a zero-dB load pull ratio for the main amplifier arrangement comprising the first and second main amplifiers 321-1, 321-2. At the same time, the third peak amplifier 330 is connected to the isolated port 3 lOd of the hybrid combiner 310 and is therefore not affecting the main amplifier with an imperfect off impedance when it is off, thereby improving the off impedance issue. Thus, the peak functionality is distributed across the hybrid coupler 310 using the three peak amplifiers 322-1, 322-2 and 330 (e.g. one balanced peak amplifier 322-1,

322-2 - e.g. using 2 transistors - and a single ended peak amplifier 330).

Table 1. Comparison Different implementation of a 1KW amplifier and 9.54dB Back Off

Table 1 shows a comparison of different architectures implementing a 9.54dB back off power amplifier. As can be observed, the classical (C.) Doherty and prior art 1 (first implementation) suffer from a high load pull ratio which limits design possibilities. Prior art lb employs the driving scheme described previously and has the same total power size of devices as an embodiment of the dBD of Figure 3. However, in the example of figure lb, half of the power of the peak amplifiers is connected to the isolated port of the hybrid coupler. Accordingly, doubling the size of such a device will result in twice the output capacitance. This makes it more difficult to match the output of the peak devices and increases the off- impedance dispersion which in turn will increase the effect of losses over a given frequency band.

Another advantage of the embodiments of the disclosure becomes apparent when the driving signals of the Main and Peak amplifiers are considered. Figure 5 shows sequential driving current signals of embodiments with 9.54 dB back off 1KW Peak Power. Figure 6 shows the phase of the driving currents plotted against output voltage. In Figure 5 and Figure 6, ‘Main’ refers to the driving signal provided by the main balanced amplifier from main amplifiers

321-1, 321-2, ‘Peak 3’ refers to the signal provided by the third peak amplifier 330 and ‘Peak 1,2’ refers to the signals provided by the peak balanced amplifier from amplifiers 322-1, 322- 2

In Figure 6 the phase of the signal provided by ‘Peak G is shown and not ‘Peak 2’. As will be appreciated, however, ‘Peak T will be 90 degrees out of phase with the signal of ‘Peak G. In an embodiment, the sequential driving process is performed according to the method shown in Figure 4. The process beings with the start (S401) of a power sweep during an RF signal cycle. At block S402, the main amplifier arrangement is switched on. In other words, power is provided from the main amplifier arrangement. In the Figure 3 embodiment, for example, this means driving the first and second main amplifiers 321-1, 321-2 via a driving signal provided at the input port 350a of the third hybrid splitter 350. The main amplifier power is increased to meet the demand as the power sweep proceeds until it reaches a predetermined level. For example, until it is greater than a threshold value. The threshold value might be the maximum output power from the main amplifier arrangement, for example. In the Figure 3 embodiment, this might be the maximum power from the first and second main amplifiers which could be 112W. If true at block S404 that output power crosses the threshold then the ‘Yes’ branch is followed to block S405. At S405 the peak amplifiers are switched on, i.e. power is provided by the peak amplifiers and power continues to be supplied from the main amplifier arrangement i.e. the main amplifier is kept switched on and providing power at the threshold (e.g. its maximum available power).

In Figure 5, ‘Peak’ denotes the drive current from the first and second peak amplifiers 322-1,

322-2 while ‘Peak dBD’ denotes the drive current from the third peak amplifier 330. The power is increased with the power at each of the first and second peak amplifiers 322-1, 322-2 being half that of the third peak amplifier 330 due to the respective difference in size (222W vs 444W). The power provided by the peak amplifiers 322-1, 322-2, 330 is increased at S406. At step S407 it is determined if the output power is at the peak envelope power i.e. the highest envelope power. If ‘Yes’ then the power sweep ends at block S408. If ‘no’, then the power provided by the peak amplifiers continues to be increase and the process returns to block S406.

Thus, it is not necessary to turn off the main amplifier to achieve the same LPR as in prior art 1, second implementation. Accordingly, by applying the sequential driving process of Figure 4 to the power amplifier of Figure 3, there is, at all power levels, the ability to control relative amplitude and phase thereby achieving the benefits that come from tracking impedances over a wide frequency range.

A further embodiment is shown in Figure 7 in which the impedance modifying elements 323a and 323b comprise a pair of matched networks (MN) and combiners which couple the output signals from the respective peak 321-1,321-2 and main amplifiers 322-1, 322-2 at the input ports 310a, 310b of the hybrid combiner 310. Further matched networks 711, 712 couple the inputs 321-la, 321-2a of the main amplifiers 321-1, 321-2 with the outputs 350b, 350c of the third hybrid splitter 350 respectively. Similarly, matched networks 721, 722 couple the inputs 322- la, 322-2a of the peak amplifiers 322-1, 322-2, with the outputs 342b, 342c of the second hybrid splitter 342 respectively. The third peak amplifier 330 is logically buttressed on one side by a matched network located between its input 330a and the output 341b of the first hybrid splitter 341 and at the other side by a matched network located between its output 330b and the isolated port 3 lOd of the hybrid combiner 310. In embodiments, the various matched networks 711, 712, 721, 722, 731, 732, 323a, 323b perform network matching to provide efficient coupling between the elements in the circuit in a manner that will be understood by those skilled in the art.

In a further embodiment, the dBD PA of Figure 3 can be modified to provide extended back off with high efficiency. Figure 8 shows a block diagram illustrating a power amplifier arrangement 800 according to an embodiment, whereby the first and second main amplifiers 321-1, 321-2 are respectively replaced by first and second Doherty amplifiers 801a, 801b.

The first and second Doherty amplifiers 801a, 801b each comprise a Doherty peak amplifier 820-1, 820-2 and Doherty main amplifier 810-1, 810-2 respectively. An impedance modifying element (e.g. a transmission delay line such as a l/4 transmission line) 830a, 830b is provided between the outputs 350b, 350c of the third hybrid splitter 350 and inputs 810- la, 810-2a of the main amplifiers 810-1, 810-2 of the Doherty amplifiers. This acts to put the signal at the main amplifiers 810-1, 810-290 degrees out of phase with the signal at the inputs 820- la, 820-2a of the peak amplifiers 820-1, 820-2 to provide a classical Doherty action. Further, for each Doherty amplifier 801a, 801b there is provided an impedance modifying element (e.g. a transmission delay line such as a l/4 transmission line) 840a, 840b interposed between the output of the main amplifier 810- lb, 810-2b and the output of the peak amplifier (‘Peakl’) 820-lb, 820-2b for matching the respective outputs i.e. phase match the outputs such that they are effectively combined at the outputs 820-lb, 820-2b. The other elements of the power amplifier arrangement 800 correspond to those of the arrangement shown in Figure 6 and operate in a substantially similar manner and accordingly the description of those elements will not be repeated here.

As each of the main amplifiers 321-1, 321-2 have been effectively replaced by a Doherty amplifier 801a, 801b the back off of the total power amplifier arrangement 800 will be extended by the Doherty back off provided by the respective Doherty amplifiers 801a, 801b.

In an embodiment, a 1KW Peak power amplifier with a 12dB back off may be designed according to the topology of Figure 8. The basic dBD is designed with 6dB Back off, and a symmetrical Doherty (main and peak amplifiers have the same power) is used as Doherty amplifier arrangements 801a, 801b adding an extra point of high efficiency at 6dB back off (referred to as Tl) in addition to the dBD point of high efficiency at back off (referred to as T2). The following table shows the power level of the different amplifiers which constitute this amplifier and the LPR achieved.

The sequential driving signals are depicted in Figure 9 and the corresponding phases of the driving signals in Figure 10. In Figure 9 and Figure 10, ‘Main DFFT refers to the driving signal provided by the main amplifiers 810-1, 810-2, ‘Peak DFFT refers to the signal provided by the peak amplifiers 820-1,820-2 and ‘Peak 1,2’ refers to the signals provided by the first and second peak amplifiers 322-1,322-2 and ‘Peak 3’ refers to the signal provided by the third peak amplifier 330. In Figure 10, the phase of the signal provided by ‘Peak G and not ‘Peak 2’ is shown. However, as will be appreciated, the signal provided by ‘Peak 2’ will be 90 degrees out of phase with the signal of ‘Peak G. The phase difference between Peak 3 and Peak 1 is -90 degrees. The phases in Figure 10 are the phases of the signals that the amplifiers deliver to the output. Although, embodiments use an arrangement of splitters, the relative phases of the driving signals can be provided and arranged in different ways to provide the same outcome. As can be seen the power is increased at the main amplifiers 810- 1, 810-2 until a first power threshold is reached at which point the ‘Peak DHT’ amplifiers 820-1, 820-2 provide power which is increased until both main 810-1, 810-2 and peak 820-1, 820-2 amplifiers of the Doherty arrangements 801a, 801b are saturated (or the power provided exceeds a threshold power value). Then, the power is provided from the distributed peaks 322-1, 322-2, 330 (‘Peak 1,2’ and ‘Peak 3’ in Figure 9) via the peak drive signal distributed by the peak distribution circuit 340 until a predetermined power level is reached (e.g. the peak envelope power).

The impedances of the amplifiers in the power amplifier arrangement 800 plotted against output power is shown in Figure 11. It can be seen that the main impedance ‘Main DHT’ (i.e. impedance of main amplifier 810-1, 810-2) is indeed changing 2:1 indicating a moderate load pull ratio for so high back off (12dB). The ‘Main DHT’ (i.e. main amplifier 810-1, 810-2) and ‘Peak DHT’ (i.e. peak amplifier 820-1, 820-2) impedances remains constant from 6dB back off to full power thanks to the distributed peak amplifier arrangement. Finally, the distributed Peak amplifier (i.e. ‘Peak 3’) 330 does not see any load pull ratio because its connection to the isolated port 3 lOd of the quadrature hybrid combiner 310.

The power efficiency (%) of the power amplifier arrangement 800 is plotted against power (W) in Figure 12. As can be seen there is a high efficiency peak T1 at 12dB back off corresponding to additional 6dB back off provided the Doherty amplifiers 801a, 801b and a second high efficiency peak T2 at 6dB back off provided by the dBD arrangement.

In the embodiment shown in Figure 8 and described above Doherty amplifiers are used for the main amplifiers 321-1, 321-2. However, in other embodiments, other amplifier topologies may be used in place of the main amplifiers 321-1, 321-2. Any amplifier topology providing high efficiency at some back off, that is at a non-zero back off level, will provide some extension of high efficiency back off. For example, either or both of the main amplifiers may be implemented as an N-Way Doherty amplifier, Chireix amplifier, a combination of Chireix and Doherty amplifier, or an Envelope Tracking Amplifier to increase the high efficiency back off. The topology of an N-way Doherty, Chireix and Envelope Tracking Amplifier would be understood by those in the art and, thus, further description is not necessary here.

In another embodiment, the circuit topology of Prior art 1 - a Balanced Single Ended Single Ended (BSS) topology - is used but with different device sizes and sequential driving according to the method already described with respect to Figure 4. A power amplifier arrangement 1300 as shown in Figure 13 is used but amplifier elements are driven such that the main and peak/auxiliary driving of Prior art 1 are reversed. The circuit is driven according to the sequential driving process of Figure 4. Further, in designing the amplifier 1300, a power size ratio between peak and main is chosen to optimize performance. This embodiment happens to be another solution of the case where the peak amplifier is implemented as balanced amplifier 1320 and a Main amplifier 1321 receives a main input driving signal at input 1321a and has an output 1321b connected to the isolated port 13 lOd of a quadrature hybrid combiner 1310. The quadrature hybrid combiner being for combining the signals from the outputs 1322- lb, 1322-2b of first and second peak amplifiers 1322-1, 1322-2 of balanced amplifier 1320 so as to provide power at an output port 1310c. A quadrature hybrid 1340 is arranged as a signal splitter which takes the peak drive signal at an input port 1340a and provides direct signal at direct port 1340b and a quadrature (-90 degree shifted) signal at quadrature port 1340c. An isolated port 1340d is terminated with a fixed impedance. The direct and quadrature signals at the output ports 1340b, 1340c are provided to the inputs 1322- la, 1322-2a of the peak amplifiers 1322-1, 1322-2. In an embodiment, the power size of the amplifiers may be: Main: 112W and Peak 888 W (2x444W) to achieve 9.54dB back of. The proposed sequential driving will allow different power ratios to be used which will introduce the flexibility to trade off the size of peak amplifiers versus the back off that can be delivered by the main amplifier arrangement.

The driving currents plotted against output voltage are shown in Figure 14. As can be seen, the main amplifier 1321 is switched on to provide power and the power provided is increased until a threshold is crossed. This corresponds to the steps S401-S404 of Figure 4, for example. The threshold may correspond to the main amplifier 1321 becoming saturated.

Once the threshold is exceeded, the peak amplifiers 1322-1, 1322-2 are switched on. That is to say power is provided from the balanced amplifier arrangement 1320 comprising the peak amplifiers 1322-1, 1322-2. The peak amplifier power is increased until some target power is reached, for example, the peak envelope power of the RF signal. Importantly, the main amplifier 1321 is not turned off and continues to provide power. This corresponds to steps S405-S408 of Figure 4, for example.

Accordingly, this embodiment solves the LPR problem, and as a result of the sequential driving shown in Figure 14 and following the process of Figure 4, allows the potential of the LMBA impedance tracking to be realized. It enables a desired back off to be achieved by balancing the size of the peak amplifiers with the main amplifier to achieve the desired back off. For example, smaller peak amplifiers can be used to reduce the off-impedance problem and the back off can be achieved by choosing a main amplifier with more back off.

In embodiments, a main amplifier with more back off may be provided by replacing the single ended main amplifier 1321 with an extended back off amplifier such as: a Chireix amplifier, a combination of Doherty and Chireix, an N-way Doherty or an Envelope tracking amplifier. In this way the back off can be extended further more. Embodiments are not limited to these examples however, and any amplifier arrangement that provides high efficiency at some back off (non-zero back off) may be substituted for the single ended main amplifier 1321.

For example, an embodiment is shown in Figure 15 wherein the main amplifier 1321 is implemented as a Doherty amplifier having a main 1510 and peak amplifier 1520. An impedance modifying element 1530 (which in this embodiment is a l/4 transmission line) is connected across the inputs 1510a, 1520a of the main and peak amplifiers 1510, 1520 in the Doherty arrangement 1321 to provide the necessary 90-degree phase difference at their inputs. The outputs 1510b, 1520b of the main and peak amplifiers 1510, 1520 are connected to respective ends of a further impedance modifying element 1540 (which in this embodiment is a l/4 transmission line) providing a 90-degree phase shift to match the outputs. The combined signal output of the main and peak amplifiers 1510, 1520 is provided to the isolated port 13 lOd of the hybrid combiner 1310 by a connection between the output port 1520b of the peak amplifier 1520 and the isolated port 13 lOd.

Another embodiment is shown in Figure 16 in which the main amplifier 1321 is implemented using an N-way Doherty amplifier comprising a plurality of power amplifiers 1610-1..1610- N. In an embodiment, the first power amplifier 1610-1 is configured as the main amplifier and the subsequent power amplifiers 1610-2..1610-N are auxiliary/peak amplifiers. The main drive signal is provided at an input port 1620a of a matched network and signal splitter 1620 which provides signal coupling and distributes the main drive signal to the inputs 1610- la..1610-lb of the power amplifiers 1610-1..1610-N. The outputs 1610-lb. 1610-Nb of the power amplifiers 1610-1..1610-N are connected to the inputs 1630-la..l630-Na of a matched network and combiner 1630 which combines the respective output signals and provides a single output 1630b to the isolated port 13 lOd of the quad coupler 1310. The auxiliary/peak amplifiers 1610-2... 1610-N are configured to be turned on at a certain power level. The staging of the turn on of the auxiliary/peak amplifiers 1610-2..1610-N may be configured such that the auxiliary/peak amplifiers are turned on at once or are staged to turn on at different power levels e.g. corresponding to efficiency peaks. The higher the number of power amplifiers 1610-1..1610-N in the N-way arrangement the further the back off may be extended but with further stages the complexity is increased. Further matched networks 1640a, 1640b couple the outputs 1340b, 1340c of the signal splitter 1340 with the inputs 1322- la, 1322-2a of the peak amplifiers 1322-1, 1322-2. In addition, matched networks 1650a, 1650b couple the outputs 1322-lb, 1322-2b of the peak amplifiers 1322-1, 1322-2 with the inputs 1310a, 1310b of the quad coupler 1310. The matched networks thereby provide efficient signal transfer between the signal splitter 1340, the balanced amplifier 1320 and the quad coupler 1310.

As mentioned above the main amplifier may alternatively be substituted with a power amplifier arrangement based on a Chireix or Envelope tracking topology. As these topologies are understood by those in the art further description is not provided. Thus, according to arrangements and methods described herein, the effect of the off impedance of the peak amplifiers may be reduced may be used and impedance control achieved over the whole power range. The off-impedance problem is minimized because smaller peak amplifiers may be used with respect to the main amplifier.

As a result of this, it is possible to increase the back off average efficiency in high power (i.e. 1KW operating at 9dB Back off) wide band (i.e. 40% Bandwidth) power amplifier designs used in modern mobile telecommunication infrastructures.

Further, the simplicity of the sequential driving opens the possibility to implement these amplifiers with simple driving schemes e.g. a simple 2 channel multi input single output power amplifier design (MISO PA) may be used.

In an embodiment of a drive circuit suitable for providing the sequential driving described above in respect of embodiments (e.g. the method of Figure 4), is provided as shown in Figure 17.

In this embodiment, a drive circuit can provide main and peak drive signals to channel 1 (main) and channel 2 (peak) inputs of the embodiments described above.

In an embodiment, the drive circuit is a controller that provides digital control to a MISO PA (Multi Input Single Output PA). Generally speaking, the controller takes a modulated signal, analyzes the wave form and determines signals to be delivered to multiple input channels 1 and 2, following the flow diagram of Figure 4, for example.

The controller 1700 comprises a base band (BB) digital signal processing unit 1720 and an RF module 1730. The BB digital signal processing unit 1720 comprises a look up table/digital pre-distorter (LUT/DPD) unit 1721 which provides respective first and second digital outputs to first and second digital -to-analog converters (DACs) 1722, 1723. The outputs of the first and second DACs 1722, 1723 are respectively provided to up-converters (e.g. IQ modulators) 1731, 1732 which in turn provide the main drive signal and peak drive signals at their outputs to be provided to channel 1 and channel 2 of the power amplifier architecture in embodiments described above. In the example of Figure 17, a modulated signal 1710 to be transmitted is represented in the form of a time domain signal that is the amplitude of, e.g., a real LTE signal in a short time interval. This signal 1710 can be processed (e.g. continually streamed and processed) inside the BB digital signal processing unit 1720 to perform signal splitting for the main and peak channels (channel 1 and channel 2). The signal splitting, which is performed according to look up tables implemented in the LUT/DPD unit 1721, is configured to process the input signal 1710 and decide which amplitude and phase should be sent to the respective channels in order to be able to reproduce the input modulated signal with the maximum fidelity and best efficiency at the power amplifier. In an example, the LUT/DPD unit 1721 can be optimized in order to provide channel 2 (which corresponds to the Peak Pas) with no signal, or a very small signal (e.g. substantially no signal), when the amplitude of the modulated signal 1710 is below a threshold value. Over the threshold value, the LUT/DPD 1721 can return a signal that increases the channel 2 peak drive signal and maintains channel 1 (corresponding to a main drive signal), at an approximately constant amplitude whilst adjusting the phase in a convenient way in order to achieve a desired impedance at the peak amplifiers. This phase control, along with some minor amplitude control, enables the impedances to be tracked over a wide frequency range and thus enables the power amplifier in embodiments to operate effectively across a wide bandwidth. Such phase and amplitude control techniques are understood by those skilled in the art and further description, therefore, is not necessary here.

After the signal is processed in the base band unit 1720 it is converted to analogue in the respective DAC units 1722, 1723 and the analogue signals provided to the up converters 1731, 1732 of the RF module 1730. The analogue signals are converted to RF by the respective mixers 1731, 1732 in the RF Module. The outputs 1730a, 1730b of the RF module 1730 are directly or indirectly connected to the two inputs of a final stage MISO (Multi input Single output amplifier) e.g. a power amplifier topology according to any of the embodiments. In an embodiment, the outputs 1730a, 1730b may be connected indirectly through drivers (not shown) in order to fit to an input power of the target power amplifier.

Thus, the driving circuit 1700 of Figure 17 may be used to provide the channel 1 (main) and channel 2 (peak) signals in any of the embodiments described herein. Further, according to an embodiment, the LUT/DPD may be configured to provide the correct main and peak drive signals for channel 1 and channel 2 respectively in accordance with the sequential driving method shown in Figure 4, for example.

Embodiments are not limited to this driving circuit topology, however. As will be appreciated by those skilled in the art other schemes and driving circuits may be used to provide main and peak driving signals.

The control method disclosed in embodiments may be implemented using a processing unit of a device. In a process of implementation, the steps of determining the driving signals, e.g. to implement the method of Figure 4, may be completed using an integrated logic circuit of hardware in the processing unit or instructions in a software or machine-readable form. These instructions may be implemented and controlled by using the processing unit and configured to cause a controller to cause a power amplifier to perform a method according to any of the embodiments described herein. So configured as to execute the power amplifier control method disclosed in embodiments, the foregoing processing unit may comprise a general- purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or another programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component; and can implement or execute each disclosed method, step, and logic block diagram in the embodiments described herein. The general-purpose processor may be a microprocessor or the processor may be any common processor, and so on. The steps with reference to the method disclosed in embodiments may be directly executed and completed by a hardware decoding processor or executed and completed by a combination of hardware and a software module in a decoding processor. The software module may be located in a mature storage medium in the art, such as a random-access memory, a flash memory, a read-only memory, a programmable read-only memory, an electronically erasable programmable memory, or a register. The storage medium is located in the memory, and the processing unit reads information in the memory, and completes the steps of the method with reference to the hardware.

In the above description the expression “peak amplifier” is used. However, as will be appreciated by those skilled in the art the equivalent expression “auxiliary amplifier” may be used as an alternative. A person of ordinary skill in the art may be aware that, in combination with the examples described in the embodiments described herein, units and algorithm steps may be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether the functions are performed by hardware or software depends on applications and design constraint conditions of the technical solutions. A person skilled in the art may use different methods to implement the described functions for each application, but it should not be considered that such implementation goes beyond the scope presented herein.

It may be clearly understood by a person skilled in the art that, for the purpose of convenient and brief description, for a detailed working process of the foregoing system, apparatus, and unit, reference may be made to the corresponding process in the foregoing method embodiments, and details are not described herein again.

In the embodiments provided, it should be understood that the disclosed system, apparatus, and method may be implemented in other manners. For example, the described apparatus embodiment is merely exemplary. For example, a plurality of units or components may be combined or integrated into another system, or some features may be ignored or not performed. In addition, the displayed or discussed mutual couplings or direct couplings or communications connections may be implemented through some interfaces. The indirect couplings or communications connections between the apparatuses or units may be implemented in electronic, mechanical, or other forms.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one position, or may be distributed on a plurality of network units. A part or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.

In addition, functional units in embodiments may be integrated into one processing unit, or each of the units may exist alone physically, or two or more units are integrated into one unit.

When the functions are implemented in the form of a software functional unit and sold or used as an independent product, the functions may be stored in a computer-readable storage medium. Based on such an understanding, the technical solutions of embodiments, or the part contributing to the prior art, or a part of the technical solutions may be implemented in the form of a software product. The computer software product is stored in a storage medium, and includes several instructions for instructing a computer device (which may be a personal computer, a server, or a network device) to perform all or a part of the steps of the methods described in embodiments. The foregoing storage medium includes: any medium that can store program codes, such as a USB flash drive, a removable hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk, or an optical disc. Embodiments can be embodied in other apparatus and/or methods. The described embodiments are to be considered in all respects as illustrative and not restrictive. The scope of the invention is indicated by the appended claims rather than by the description and figures herein. All changes that come within the meaning and range of equivalency of the claims are to be embraced within their scope.