PRE-LOAD TECHNIQUES FOR IMPROVED SEQUENTIAL MEMORY ACCESS IN A MEMORY DEVICE

Title:

PRE-LOAD TECHNIQUES FOR IMPROVED SEQUENTIAL MEMORY ACCESS IN A MEMORY DEVICE

Document Type and Number:

WIPO Patent Application WO/2021/184714

Kind Code:

A8

Abstract:

Devices and techniques for improving memory access operations of a memory device are provided. In an example, a method can include loading multiple LBA-to-physical address (L2P) regions of an L2P table from memory arrays of the memory device to a mapping cache in response to determining the LBA of the memory access command is not within the L2P region including of a mapping cache. When the memory access command is a sequential command, the multiple L2P regions loaded to the mapping cache can provide improved memory access performance.

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Inventors:

ZHAO BIN (CN)
DUAN XINGHUI (CN)
HUANG JIANXIONG (CN)

Application Number:

PCT/CN2020/116462

Publication Date:

October 13, 2022

Filing Date:

September 21, 2020

Export Citation:

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Assignee:

MICRON TECHNOLOGY INC (US)

International Classes:

G06F12/02

Attorney, Agent or Firm:

LEE AND LI-LEAVEN IPR AGENCY LTD. (CN)

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