Title:
PREPARATION METHOD FOR SEMICONDUCTOR STRUCTURE, SEMICONDUCTOR STRUCTURE, AND CAPACITOR STRUCTURE
Document Type and Number:
WIPO Patent Application WO/2023/000373
Kind Code:
A1
Abstract:
Provided in the embodiments of the present application are a preparation method for a semiconductor structure, a semiconductor structure, and a capacitor structure. The preparation method comprises: providing a substrate having a plurality of blind vias or trenches in a surface thereof; forming a filling layer in the plurality of blind vias or trenches, with the top surface of the filling layer being flush with the top surface of the substrate; and forming a covering layer on the top surface of the filling layer and the top surface of the substrate, wherein the covering layer comprises at least one stacked structure, each stacked structure comprising a first covering layer and a second covering layer, and a doped material source of the first covering layer being different from that of the second covering layer. In this way, the covering layer is realized using the stacked structure containing the first covering layer and the second covering layer, which can avoid the problem of stress accumulation during deposition, improve the uniformity and surface roughness of the covering layer, and balance the resistance of the structure, thereby improving the performance of the semiconductor structure.
Inventors:
CHIU TING-CHUNG (CN)
Application Number:
PCT/CN2021/109675
Publication Date:
January 26, 2023
Filing Date:
July 30, 2021
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
H01L21/8242; H01L27/108; H01L49/02
Foreign References:
| US20050042889A1 | 2005-02-24 | |||
| US20030027386A1 | 2003-02-06 | |||
| CN1674259A | 2005-09-28 | |||
| CN103390541A | 2013-11-13 |
Attorney, Agent or Firm:
CHINA PAT INTELLECTUAL PROPERTY OFFICE (CN)
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