FIELD OF THE INVENTION

The present invention pertains to a process comprising the successive steps of forming a perforated metal or metalloid oxide film onto a silicon substrate from a sol-gel layer, then chemically treating said film before depositing a layer of inorganic material to obtain an organized layer of nanoparticles onto which semi-conducting nanowires may then optionally be grown. This invention is further directed to the structure thus obtained, comprising a network of semi-conducting nanoparticles or nano wires, and to its uses.

BACKGROUND OF THE INVENTION

It has been known that to produce nanowires and nanopattemed surfaces for use in electronic, optics, photocatalysis, photovoltaic and magnetic devices, inter alia, by depositing certain metal particles within the pores of a porous metal oxide film coated on a substrate. These metal particles may themselves have properties needed for some applications or they may form catalytic sites for the further growth of nano wires. The properties of these devices are linked to the regularity of the array of pores and the pore size. It has indeed been known that physicochemical heterogeneities are an important issue in the design of complex components used in high-tech technologies.

Usual techniques for obtaining this array of particles consists of evaporating a layer onto the substrate and then forming a specific pattern therein by lithography to form the final particles after a thermal treatment of the patterned layer. The drawback of this technique is that the array of particles lacks homogeneity and/or has limitations to be used on large scale. For instance, Electron-beam lithography or Focused Ion Beam lithography provide a homogeneous array of particles but on a very small scale.

To overcome this drawback, it has been suggested to form a perforated metal oxide film via the sol-gel route onto a silicon wafer, wherein the perforations provide nanosites for heterogeneous nucleation (M. Kuemmel et ah, Chem. Mater. 2007, 19, 3717-3725) or influence the 3D growth of subsequently deposited layer (A. Fisher et ah, Small 2006, 2, No. 4, 569-574).

However, the inventors have shown that the deposition of catalytic nanoparticles onto this film resulted in a higher affinity of the nanoparticles with the oxide layer formed by the sol-gel route than with the native silicon oxide layer remaining in the bottom of the perforations. These nanoparticles thus do not specifically accumulate within the perforations, which negatively affects the accuracy of their distribution.

WO 2008/034471 describes a process for producing a porous nanostructure suitable for the fabrication of nanoscale patterns or of nanowires. This nanostructure is obtained by forming a porous oxide layer bearing nanoholes on an aluminum substrate, for instance by anodization of aluminum, then etching the bottom of said holes with a basic zincate solution to form a thin zinc film in the bottom of the pores. Nickel nano wires are then formed by electrochemical deposition of nickel within said pores.

A similar process is disclosed in the Thesis of Thomas David (https ://tel.archives- ouvertes.fr/tel-003430l4). It is explained therein that this process has a number of limitations (see from page 75): difficulty for the gaseous precursors to reach the bottom of the pores with a risk of obstructing the pores, poor control of the orientation of nanowires...

Finally, CN 106400084 relates to a process for preparing nickel nanowires, using a porous sol- gel alumina template. The latter is electrochemically prepared and, is then mixed with nickel precursor under microwave conditions, which allows nickel nanowires to grow into the porous alumina template. The invention enables access to metallic nanowires but not to semi conducting nano wires.

Therefore, there remains a need to provide a cost-effective solution to overcome the drawbacks of the prior art above. SUMMARY

The inventors have shown that the above need may be satisfied by providing a process in which a regularly perforated metal or metalloid oxide layer is deposited onto a silicon substrate via the sol-gel route and is then subjected to treatment with a specific etching agent. This etching agent allows removing the native silicon oxide layer that has been shown to remain in the bottom of the perforations and to negatively affect the affinity of the nanoparticles with said holes, compared to the metal oxide layer. Removal of the native silicon oxide layer thus favours the deposition of nanoparticles within the pores by increasing the affinity of the nanoparticles with the pores.

This process thus provides a homogeneous array of nanoparticles on a silicon substrate, wherein said nanoparticles are selectively deposited in regularly-arranged holes. It further provides a cost-effective process for the formation of a metal or metalloid oxide layer comprising regularly-arranged perforations. This process may further be applied to the deposition of nanoparticles over large surfaces. This straightforward process comprises a small number of steps, which can be implemented successively without the need for any additional intermediate treatment steps.

This invention is thus directed to a process comprising the following successive steps:

(a) forming a perforated metal or metalloid oxide film onto a silicon substrate from a sol-gel layer,

(b) chemically treating said perforated oxide film with hydrofluoric acid for a suitable period of time, so as to remove native silicon oxide from the bottom of said perforations,

(c) depositing a layer of inorganic material selected from transition metals, post-transition metals, metalloids, non-metallic inorganic elements, and combinations thereof onto the assembly thus obtained, under conditions allowing to obtain an organized layer of nanoparticles,

(d) optionally further subjecting said assembly to a thermal and/or mechanical treatment, for improving the spatial organization of the nanoparticles forming the inorganic layer, and

(e) optionally growing semi-conducting nano wires onto said nanoparticles. This invention further pertains to a structure comprising a network of semi-conducting nanoparticles or nanowires, obtainable by the above process.

It further pertains to a structure comprising a network of nanoparticles or nanowires made of a semi-conducting material, obtainable by the above process, said nanoparticles or nanowires being localized into perforations of a perforated metal or metalloid oxide film, and said perforated metal or metalloid oxide film being onto a silicon substrate.

It is also directed to the use of this structure for manufacturing floating gate memory devices, quantum dots for lasers, optoelectronic devices, photovoltaic devices or field-effect transistors or for in analytic methods such as surface-enhanced Raman scattering (SERS).

DETAILED DESCRIPTION

In the process of this invention, the silicon substrate is first coated with a sol-gel layer formed from a solution of metal or metalloid oxide precursor(s).

The expression "metal oxide precursor(s)" refers to any metal oxide precursor, metalloid oxide precursor or combination thereof, which is conventionally used in sol-gel processes. The precursors may for instance be selected from the group consisting of inorganic salts, organic salts or alkoxides of at least one metal or metalloid or of a combination of at least one metal with at least one metalloid. Examples of inorganic salts are halides (fluorides, chlorides, bromides or iodides, especially chlorides), oxychlorides and nitrates. Organic salts may be selected from oxalates and acetates, for instance, while alkoxides are typically of formula (RO) _n M where M denotes the metal or metalloid, n represents the number of ligands linked to M which corresponds to the valency of M and R represents a linear or branched alkyl chain having from 1 to 10 carbon atoms or a phenyl group; organometallic compounds of formula X _y R^M wherein M represents a metal or metalloid, X represents a hydrolysable group chosen from halogen atoms, acrylate, acetoxy, acyl or OR' groups where R' is a linear or branched alkyl group comprising from 1 to 10 carbon atoms or a phenyl group, R ¹ represents a non- hydrolysable group selected from optionally perfluorinated linear or branched alkyl groups comprising from 1 to 10 carbon atoms or a phenyl group, and y and z are integers chosen so that y + z is equal to the valency of M . The metals may be selected from titanium, hafnium, zirconium, aluminum, copper, iron, scandium, vanadium, chromium, manganese, cobalt, nickel, copper, yttrium, niobium, molybdenum, technetium, ruthenium, rhodium, palladium, silver, tantalum, tungsten, rhenium, osmium, iridium, platinum, gold, rutherfordium, dubnium, seaborgium, bohrium, hassium, copemicium, cerium, erbium, europium, gadolinium, holmium, lanthanum, lutetium, neodymium, praseodymium, promethium, samarium, scandium, terbium, thulium, ytterbium, yttrium and their mixtures, whereas suitable metalloids include for instance silicon, selenium and tellurium. Titanium, silicon and zirconium are preferred for use in thus invention. Titanium is especially preferred.

Examples of silicon precursors are tetraethoxysilane (TEOS), tetramethoxysilane (TMOS), tetrapropoxysilane, methyltriethoxysilane, dimethyldimethoxysilane, allyltrimethoxysilane, propyltriethoxysilane, phenyltriethoxysilane, 1 ,4-bis(triethoxysilyl)benzene, vinyltriethoxysilane, phenylaminomethyltriethoxysilane (PAMS), triethoxysilane, triethoxy(octyl)silane, methyltrimethoxysilane, phenyltrimethoxysilane and methyltriisopropoxysilane, preferably tetraethoxysilane (TEOS); examples of titanium precursors are TiCl _4, Ti(OPr) ₄ , Ti(N0 ₃ ) ₄ , Ti(S0 ₄ ) ₂ and titanium acetate. The metal or metalloid precursors may further be present in a hydrated form. Precursors of different metals or metalloids or precursors of a combination of at least one metal with at least one metalloid may be used, to obtain ceramics in the form of complex oxides with a defined stoechiometry.

To form the solution used in this invention, the precursors are typically combined with a solvent selected from water, mono- or dihydric alcohols, such as methanol, ethanol, n-propanol, ethylene glycol, propylene glycol or a mixture thereof. Water combined with organic solvent(s) is generally used in the case of inorganic precursors and organometallic precursors. In the former situation, ethanol is preferably present in the solution in order to improve the wetting of the substrate, disperse the precursors and reduce the kinetics of their hydrolysis to avoid crosslinking. The solution may additionally comprise a catalyst, which may be selected from basic catalysts (such as NH ₃ ) and acidic catalysts, preferably a small and volatile acid (such as acetic acid or hydrochloric acid), less preferably a non-volatile acid (such as nitric acid). The solution may also comprise surfactants, such as a cationic surfactant, to stabilize the colloidal solution or“sol” formed after hydrolysis and polymerization of the precursors. Chelating agents may further be provided in the solution, although not needed according to this invention.

This solution may be applied to the silicon substrate by any appropriate means, including by dip-coating, spin-coating or spray-coating, preferably by dip-coating, so as to form a sol-gel layer.

In the process of the invention, the sol-gel layer deposited on the substrate is subjected to suitable conditions enabling the formation of a perforated metal or metalloid oxide film onto the substrate. The thickness of said film may be adjusted by tuning different parameters such as the temperature, the speed of deposition and/or the concentration of the solution.

In a particular embodiment, the sol-gel layer is formed from a solution of metal or metalloid oxide precursor(s) which further comprises a pore-forming polymer, and the process of this invention comprises the substeps of:

(al) depositing a sol-gel layer containing metal or metalloid oxide precursors and a pore forming polymer onto a silicon substrate,

(a2) subjecting said sol-gel layer to a thermal or chemical treatment under conditions allowing the condensation of said metal or metalloid oxides and the removal of the polymer, so as to obtain a perforated oxide layer.

Said pore-forming polymer may be selected from amphiphilic block copolymers that are able to form micelles by evaporation-induced self-assembly. Such block copolymers are block copolymers of poly(ethylene oxide) with a polyolefin or polypropylene oxide); block copolymers of polystyrene with poly(ethylene oxide), poly(lactic acid) or polyinylpyridine; and their mixtures. Examples of such block copolymers are (polystyrene)-b lock-polyethylene oxide), polybutadiene)-block-polyethylene oxide), [poly(ethylene-co-butadiene)-block- polyethylene oxide)], propylene-based elastomer)-b lock-polyethylene oxide), polystyrene)- block-polylactic acid), polystyrene)-block-poly(4-vinyl pyridine)), polyethylene oxide)- block-polypropylene oxide)-block-polyethylene oxide), and mixtures thereof. These amphiphilic pore-forming block copolymers comprise a hydrophilic block which interacts with inorganic precursors and a hydrophobic block which forms perforations. The size of the perforations may thus be adjusted by selecting the appropriate polymer.

Alternatively, said pore-forming polymer may be selected from polymer microspheres such as polystyrene microspheres.

In a preferred embodiment, said pore-forming polymer is selected from amphiphilic block copolymers that are able to form micelles by evaporation-induced self-assembly. The thickness of the layer may be optimized so that a monolayer of micelles is obtained. The thickness of said monolayer of micelles is typically around 10 nm. To obtain said monolayer of micelles, the temperature in step (al) may be comprised between 20 and 80 °C, and the dip-coating speed of deposition may be comprised between 0.5 and 4 mm/sec. Moreover, the desired density of perforations may be obtained by adjusting the volume ratio of inorganic precursors to block copolymer.

The temperature of the thermal treatment in step (a2) may be comprised between 200 and 500°C, preferably between 200 and 350 °C, depending on the temperature at which said pore- forming polymer decomposes. For example, the temperature typically applied to remove (polyethylene oxide)-block-(polypropylene oxide)-block-(polyethylene oxide) is around 250 °C. In addition, in case the pore-forming polymer comprises polystyrene microspheres, the temperature in step (a2) may be of around 350°C. Alternatively, the pore-forming polymer may be removed by a chemical treatment or an ozone treatment. Ammonia may thus be used to condensate the inorganic precursors and the polymer may then be removed by extraction with a suitable solvent.

The removal of the pore-forming polymer leads to perforations. The diameter and the density of perforations is typically given by the size and the density of the micelles formed in the sol- gel layer. The diameter of the perforations may be comprised between 2 and 100 nm, preferably between 7 and 50 nm. The density of perforations may be comprised between 4.10 ⁸ and 4.10 ¹² perforations / cm ² , preferably between 4.10 ⁹ and 4.10 ¹¹ perforations / cm ² , for instance 4.10 ¹⁰ perforations / cm ² . A perforated metal or metalloid oxide film is thus formed onto the substrate. In another embodiment, this perforated film may be obtained by soft nanolithography. In this case, step (a) of the process of this invention comprises the substeps of:

(al) providing a solution of metal or metalloid oxide precursors,

(a2) applying said solution onto a silicon substrate to form a film,

(a3) equilibrating the film with the atmosphere under adjusted solvent vapor pressure,

(a4) applying a soft structured mould provided with cavities onto said film to provide an assembly such that said film fills up the cavities of the mould, and maintaining said assembly under solvent vapor,

(a5) thermally treating said assembly so as to rigidity the gel film thus obtained,

(a6) removing the mould to obtain a silicon substrate coated with a patterned gel, and

(a7) curing said patterned gel so as to obtain a perforated metal or metalloid oxide film on said silicon substrate,

wherein the solvent uptake of the film is adjusted to 10 to 50% vol., preferably between 15 and 40% vol., by varying the vapor pressure in a volatile solvent at the vicinity of the gel during steps (a3) and (a4).

(a8) optionally removing a potential residual layer by any appropriate chemical or physical etching for instance Reactive Ion Etching (RIE) to obtain perforations in the metal or metalloid oxide film on said silicon substrate

Steps (al) and (a2) may be performed as described previously.

The mould used in step (a4) is typically obtained as a negative copy from a master template. The master template itself may be firstly fabricated from silicon or any other suitable material such as glass, metal oxide(s), polymers, hybrid materials and composite materials. It may be manufactured by electron beam lithography (EBL), Focused Ion Beam lithography (FIB) or any other suitable patterning technology. Then, the surface of the master may be treated to form an anti-adhesive layer thereon. The liquid mould material may then be spin coated or casted into the master template to duplicate a patterning layer. The material is usually degassed in a low pressure vacuum chamber. Subsequently, a backplane or a flexible layer may be bonded to the patterned layer. Thermal or UV curing is then generally performed in order to reduce roughness and to avoid a build-up of tension because of thermal shrinkage. The replicated mould is left to cool to room temperature and carefully peeled off from the master template. It is preferred that the mould is degassed before demoulding from the master template, for instance in a pumped dessicator.

Examples of materials that may be used for the manufacture of the mould are silicone elastomers (crosslinked polysiloxanes) that may be obtained by mixing a polysiloxane bearing reactive (such as hydride or vinyl) groups with a crosslinking silicone oligomer. Such moulds are usually referred to as "PDMS moulds".

A key feature of this embodiment of the invention is that the replication step conducted by applying the mould onto the film is performed under solvent vapor and that the solvent uptake of the sol-gel film is adjusted to 10 to 50% vol., preferably to 5 to 40% vol., for instance to 25- 35 % vol., by varying the relative pressure of the solvent. The mould has typically been degassed a few minutes before the replication step and its porosity is thus empty enough to act as a "sponge" which pumps the solvent contained into the sol-gel film while the resist sol-gel is sucked within the cavities of the patterned mould, i.e. inside the protrusions of the mould. There is thus no need to apply high pressure to the mould during replication. Specifically, according to a preferred embodiment of this invention, the pressure applied to the mould during the replication step described above that of the weight of the mould only (i.e. typically less than 10 g/cm ² ), so as to limit short-range deformations in the nanostructures formed from the film. Thus, no additional pressure is applied to the mould.

In order to reach the above uptake values, a calibration step is usually performed before conducting the process of this invention. For this purpose, the film is deposited on the substrate as described before, and placed in a chamber supplied with a dry air flow and a mixed flow of air and solvent. The solvent is a volatile solvent that may be selected from water, ethanol, isopropanol, acetone, THF, hexane, toluene and any other suitable solvent. The solvent relative pressure is varied by changing the relative flow rates of dry air and air/solvent (P/P ₀ = 1) and the volume of the film is measured for each value of the relative pressure by any appropriate means, such as by ellipsometry. A curve is thus plotted, which may be used while conducting the process of this invention to determine the solvent relative pressure that should be applied during the replication step. Importantly, the above process is conducted, until this point, under mild pressure and temperature conditions, especially ambient pressure and temperature.

In the next step of this embodiment of the process according to this invention, the assembly formed by the mould and the coated substrate is thermally treated. The duration and temperature of this thermal treatment may be adjusted to any suitable range for obtaining a gelled film which displays preference adherence to the substrate compared to the mould and sufficient rigidification to avoid collapsing of the pattern after unmoulding. Depending on the constituents of the sol-gel solution, the treatment may for instance be performed at a temperature of from 25 to 200°C for typically between 1 to 10 minutes. This drying step also allows the evaporation of part of the solvent present in the gel, further promoting its condensation.

The mould is then removed to obtain a substrate coated with a patterned gel which may have started to solidify and this gel is further densified by curing so as to obtain a patterned metal or metalloid oxide material on said substrate. This curing (or annealing) step results in a complete removal of the solvent present in the colloidal solution, of the solvent absorbed by the film, of the organic by-products generated by the precursors and of the polymer(s) that may be present in the sol-gel solution. The duration and temperature of this curing treatment may be adjusted to any suitable range, depending on the constituents of the colloidal solution, so as to obtain constant dimensions of the pattern and for instance from 200 to 800°C.

As mentioned previously, step (a) of the process according to the invention, whatever its embodiment, gives access to a perforated metal or metalloid oxide film onto the silicon substrate. The thickness of said film is typically comprised between 3 and 30 nm, preferably between 5 and 20 nm. The film has perforations opening to its external surface (which correspond to the protrusions of the patterned mould in the embodiment described above), through which a thin layer of native oxide, typically a few nanometers thick, is found on the substrate. The diameter of the perforations is advantageously higher than the thickness of the film constituted of said perforations.

Step (b) of the process according to the invention consists of chemically treating said perforated oxide film with hydrofluoric acid for a suitable period of time, so as to remove native silicon oxide from the bottom of said perforations. Said oxide film is advantageously more resistant to hydrofluoric acid etching than native silicon oxide. Hydrofluoric acid is advantageously used as an aqueous hydrofluoric acid solution. The concentration of the hydrofluoric acid solution may be comprised between 1 and 5 wt. %, preferably 1.5 and 3 wt. %, for instance 2 wt. %. The film obtained in step (a) may be treated with hydrofluoric acid typically for 2 seconds to 5 minutes, preferably from 10 to 40 seconds, for instance during 20 seconds. In a particular embodiment, the perforated metal or metalloid oxide film obtained in step (a) is a perforated titanium oxide film. The substrate is then quickly rinsed and dried, and is kept under inert atmosphere in order to delay the oxidation of the bare silicon surface.

The higher etching rate of hydrofluoric acid for the native silicon oxide layer present on the substrate than for the oxide film allows a higher heterogeneity promoting the embedding of an inorganic material into the perforations. Said inorganic material is deposited onto the assembly obtained in step (b), under conditions allowing to obtain an organized layer of nanoparticles (localized into perforations).

Said inorganic material deposited in step (c) may be a transition metal, a post-transition metal, a metalloid, a non-metallic inorganic element, or combinations thereof. Said inorganic material may be semi-conducting or not.

Examples of transition metals are vanadium, chromium, manganese, iron, cobalt, nickel, copper, zinc, cadmium, silver, gold, palladium, molybdenum, niobium, zirconium, yttrium, tungsten, tantalum, osmium, iridium and platinum, preferably gold.

Examples of post-transition metals are gallium, aluminum, tin, indium, lead and bismuth, preferably gallium.

Examples of metalloids are silicon, germanium, arsenic, tellurium and antimony, preferably silicon and germanium.

Examples of non-metallic inorganic elements are selenium, sulfur and phosphorus.

Said inorganic material deposited in step (c) may be a III-V semiconductor.

A III-V semiconductor refers to a semi-conducting material composed of one or several elements of column III of the periodic table, and one or several elements of column V of the periodic table.

Examples of elements of column III of the periodic table are boron, aluminum, gallium and indium. Examples of elements of column V of the periodic table are arsenic, phosphorus, nitrogen, antimony, and bismuth.

Preferably, said inorganic material deposited in this step (c) is selected from the group consisting of Si, Ge, Au and Ga.

The deposition of inorganic material in step (c) may be carried out by vacuum-sputtering or molecular beam epitaxy. The speed of deposition may be comprised between 0.1 nm/min and 50 nm/min. The temperature in step (c) is advantageously comprised between 300 and 1000 °C, preferably between 400 and 800 °C. Several temperature steps may be used in step (c). In a particular embodiment, the assembly is stabilized at a first temperature Tl comprised between 300 and 550 °C, preferably 450 °C, for 10 min to 1 hour, preferably 15 to 30 min, for instance 20 min, and then a second temperature T2 comprised between 550 and 900 °C, preferably between 600 and 800°C, such as 700 °C, is applied for the deposition. The temperature slope from Tl to T2 is advantageously comprised between 10 and 100 °C/min, preferably 30 to 50 °C/min, for instance 40 °C/min. In another particular embodiment, only one temperature Tl comprised between 300 and 550 °C, preferably between 400 and 500 °C, for instance 450 °C, is applied for 10 min to 1 hour, preferably from 20 to 40 min, for instance during 30 min, throughout step (c). The temperature in step (c) may be dependent on the size of the perforations. For instance the optimal temperature is 650°C for the deposition on a layer with perforations of 20 nm in diameter whereas the optimal temperature is 800°C for perforations of 7 nm.

Step (c) may advantageously be carried out under ultra-high vacuum conditions, namely at a pressure lower than 1.33.10 ⁵ Pa, preferably at a pressure of l .33xl0 ¹⁰ Pa or less. Step (c) may advantageously be carried out in an epitaxial chamber or in a sputtering chamber.

To improve the spatial organization of the nanoparticles forming the inorganic layer, the assembly obtained in step (c) may be further subjected to a thermal and/or mechanical treatment. In a particular embodiment, the assembly obtained in step (c) is further subjected to a thermal treatment. Said thermal treatment advantageously consists of maintaining the temperature of deposition used in step (c) for a suitable period of time. Said period of time may be comprised between 5 min and 1 hour, preferably 10 and 30 min, more preferably 20 min. In another particular embodiment, the assembly obtained in step (c) is further subjected to mechanical treatment. Said mechanical treatment is typically a cleaning of the surface to remove the particles potentially remaining on a surface that is not silicon, by gentle rubbing with a fabric with a typical force comprised between 0.1 to 5 N/cm ² , preferentially 0.75 N/cm ² .

The process according to the invention gives access to a highly organized network of homogeneous nanoparticles localized into the perforations. Preferably, one perforation contains one nanoparticle. Said process may be applied on a large scale, such as the scale of a silicon wafer, for instance 8 inches.

The network of inorganic nanoparticles obtained according to the process of the invention may be used per se or may be used for growing nanowires onto said nanoparticles. The inorganic nanoparticle may indeed act as a catalyst for the growth of a nanowire, which may be made of the same material as the nanoparticle catalyst or of a different material. Typically, germanium nanoparticles may be used as such, whereas gold and gallium nanoparticles will rather be used as catalysts for growing nanowires. Said nanowires may be made of any semi-conducting material such as silicon, germanium, an alloy of silicon and germanium (SiGe), or semi conducting materials from group III-IV such as gallium nitride (GaN), gallium sulfide (GaS) or gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) and the associated ternary alloys, or from group II- VI such as zinc oxide (ZnO), cadmium sulphide (CdS), cadmium selenide (CdSe), zinc sulphide (ZnS), zinc selenide (ZnSe), zinc telluride (ZnTe) and the associated ternary alloys. In a particular embodiment, the substrate and the nanowires are made of the same material, namely silicon. In another particular embodiment, the nanowires are made of a germanium-rich shell and a silicon-rich core. In another particular embodiment, the nanowires are made of a III-V semiconductor.

In yet another particular embodiment, the nanoparticles and the nanowires grown onto these nanoparticles are made of the same material, namely a III-V semiconductor. More specifically, in such an embodiment, the network of III-V semiconductor nanowires may be obtained by implementing a process comprising the following successive steps: (a’) forming a perforated metal or metalloid oxide film onto a silicon substrate from a sol-gel layer,

(b’) chemically treating said perforated oxide film with hydrofluoric acid for a suitable period of time, so as to remove native silicon oxide from the bottom of said perforations,

(c’) depositing a layer of III-V semiconductor onto the assembly thus obtained, under conditions allowing to obtain an organized layer of III-V semiconductor nanoparticles (localized into the perforations), and

(d’) growing III-V semiconductor nanowires onto said III-V semiconductor nanoparticles; and wherein, steps (c’) and (d’) are preferably fused.

The invention also relates to a structure which comprises a network of nanoparticles or nanowires made of a semi-conducting material, obtainable by the process of the invention, said nanoparticles or nanowires being localized into perforations of a perforated metal or metalloid oxide film, and said perforated metal or metalloid oxide film being onto a silicon substrate.

The size and the shape of the structure according to the invention can be suitably chosen by the skilled artisan, particularly with respect to the application that is foreseen. For instance, the silicon substrate of the structure according to the invention can be a silicon wafer. The surface of the silicon substrate may be partially or completely, preferably completely, coated with the perforated metal or metalloid oxide film, with the perforations containing the nanoparticles or nano wires.

In a preferred embodiment, said semi-conducting material is selected from the group consisting of silicon, germanium, gallium, and alloys thereof.

In a particular embodiment, said metal or metalloid oxide is selected from the group consisting of titanium oxide, silicon oxide, zirconium oxide, and combinations thereof, preferably titanium oxide.

In another particular embodiment, the diameter of said perforations is comprised between 2 and 100 nm, preferably between 7 and 50 nm. In another particular embodiment, the density of said perforations is comprised between 4.10 ⁸ and 4.10 ¹² perforations/cm ² , preferably between 4.10 ⁹ and 4.10 ¹¹ perforations/cm ² .

In another particular embodiment, the thickness of said perforated metal or metalloid oxide film is comprised between 3 and 30 nm, preferably between 5 and 20 nm.

In a preferred embodiment, one perforation contains one nanoparticle or nanowire.

The density and diameter of nanoparticles or nano wires is advantageously of the same order as the density and diameter of the perforations into which they are contained. Preferably, the ratio of the diameter of nanoparticles or nanowires to the diameter of the perforations into which they are contained, is comprised between 0.8 and 1, preferably between 0.9 and 1, more preferably between 0.95 and 1, still more preferably between 0.98 and 1. Preferably, the ratio of the density of nanoparticles or nanowires to the density of the perforations into which they are contained, is comprised between 0.8 and 1, preferably between 0.9 and 1, more preferably between 0.95 and 1, still more preferably between 0.98 and 1.

The growth of nano wires is advantageously achieved according to the Vapor Liquid Solid (VLS) process using chemical vapor deposition on an oriented substrate, which is well known to the skilled artisan. Said process consists of depositing the material forming the nanowires as a chemical vapor, which absorbs onto the liquid nanoparticles and diffuses therein, until it precipitates by nucleation at the liquid/solid interface, at the surface of the substrate, thus creating an anisotropic growth of nanowires. The length of the nanowires may be comprised between 100 nm and 100 pm, preferably between 500 nm and 50 pm, more preferably between 1 pm and 10 pm.

In a particular embodiment, the liquid nanoparticle and the material forming the nanowires form an eutectic mixture at a suitable temperature. Said temperature is the temperature at which the growth of nanowires is carried out. For example, gold and silicon form an eutectic mixture at 363 °C. The growth of nanowires made of a germanium-rich shell and a silicon-rich core may be obtained according to a typical VLS process using chemical vapor deposition of silicon and germanium, followed by a thermal oxidation of silicon-germanium nano wires. The temperature of said thermal oxidation may be comprised between 600 and 950 °C, preferably 750 °C, and may be applied for 20 min to 2 hours.

The diameter and the density of nano wires obtained according to the VLS process are typically of the same order as the diameter and the density of the perforations in which they grow.

The network of nanoparticles or nanowires obtained according to process of the invention, or the structure according to the invention, may be used for manufacturing floating gate memory devices, quantum dots for lasers, optoelectronic devices, photovoltaic devices or field-effect transistors or for in analytic methods such as surface-enhanced Raman scattering (SERS).

EXAMPLES

This invention will be better understood in light of the following examples which are given for illustrative purposes only and do not intend to limit the scope of the invention, which is defined by the attached claims.

Example 1 : Deposition of Ge nanoparticles onto a Ti0 ₂ perforated layer

A sol-gel solution consisting of TiCl _{4 :} EtOH : H ₂ 0 : PB-b-PEO copolymer (Polymer Source ^® ) in a molar ratio of 1 : 160:42:0.002 was used to obtain a coating on a silicon substrate by dip- coating at 1 mm/s in controlled chamber (T = 40°C, RH < 20%), under conditions allowing to obtain a film thickness of about 10 nm. This sample was heated to 400°C for lh, in order to crystallize Ti0 ₂ into its anatase form and to remove the copolymer.

The film thus obtained had perforations opening to its external surface, through which a thin layer (a few nanometers thick) of silicon oxide on the silicon substrate can be seen. This sample is then dipped during 20 seconds into a diluted HF solution, comprising 5 ml of HF 40% in 95 ml of water. The sample is then quickly placed under ultra-high vacuum (10-12 torr) in an epitaxy chamber. It is first heated to 450°C for 20 min, in order to remove possible contaminants, and then brought to 650°C in 5 min. The sample is then kept at 650°C during the deposition of 2 nm germanium. This temperature is maintained for 20 more minutes at the end of deposition. Under thermal stress, germanium is redistributed and organizes in the form of nanoparticles within the perforations of the oxide network. The final state of the material consists in an organized network of nanoparticles which are homogenous both in size and in large scale spacing.

Example 2 : Deposition of Au nanoparticles onto a T1O2 perforated layer

A sol-gel solution consisting of TiCl _{4 :} EtOH : H ₂ 0 : PB-b-PEO copolymer (Polymer Source ^® ) in a molar ratio of 1 : 160:42:0.002 was used to obtain a coating on a silicon substrate by dip- coating at 1 mm/s in controlled chamber (T = 40°C, RH < 20%), under conditions allowing to obtain a film thickness of about 10 nm. This sample was heated to 400°C for lh, in order to crystallize Ti0 ₂ into its anatase form and to remove the copolymer.

The film thus obtained had perforations opening to its external surface, through which a thin layer (a few nanometers thick) of silicon oxide on the silicon substrate can be seen. This sample is then dipped during 20 seconds into a diluted HF solution, comprising 5 ml of HF 40% in 95 ml of water.

The sample is then quickly placed into a vacuum chamber where a gold layer (2 nm thick) is sprayed thereon. The sample is then placed under ultra-high vacuum (10-12 torr) in an epitaxy chamber and heated to 450°C for 30 min, in order to turn the planar gold layer into organized gold nanoparticles and to form a Au-Si alloy corresponding to the eutectic composition of this mixture. A mechanical cleaning process is then performed to remove the particles present on the surface of the perforated oxide layer, thereby obtaining the desired organization.

Although this invention has been described above with reference to specific embodiments, it should be noted that various alternatives may be contemplated by the skilled artisan, such as using a different substrate than silicon, for instance germanium or gallium sulfide, especially in the case where nanowires having the same chemical composition should be grown thereon.