SCALED SPIN HALL DEVICE WITH FIELD ASSIST

BACKGROUND

[0001] Embedded memory with state retention can enable energy and computational efficiency. However, leading spintronic memory options, for example, spin transfer torque based magnetic random access memory (STT-MRAM), suffer from the problem of high voltage and high write current during the programming (e.g., writing) of a bit-cell. For instance, large write current (e.g., greater than 100 μΑ) and voltage (e.g., greater than 0.7 V) are required to write a tunnel junction based magnetic tunnel junction (MTJ). Limited write current also leads to high write error rates or slow switching times (e.g., exceeding 20 ns) in MTJ based MRAM. The presence of a large current flowing through a tunnel barrier leads to reliability issues in magnetic tunnel junctions.

BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.

[0003] Fig. 1 illustrates a device having an in-plane magnetic tunnel junction (MTJ) stack coupled to a spin orbit coupling interconnect.

[0004] Fig. 2A illustrates a cross-section of the spin orbit coupling interconnect with electrons having their spins polarized in-plane and deflected up and down resulting from a flow of charge current.

[0005] Fig. 2B illustrates a plot showing write energy-delay conditions for one transistor and one magnetic tunnel junction (MTJ) with spin Hall effect (SHE) material compared to traditional MTJs.

[0006] Fig. 2C illustrates a plot comparing reliable write times for spin Hall MRAM and spin torque MRAM.

[0007] Fig. 3A illustrates a three dimensional (3D) view of a device having an MTJ stack coupled to a positive spin Hall angle electrode with field assist, according to some embodiments of the disclosure.

[0008] Fig. 3B illustrates a top view of the device of Fig. 3A, according to some embodiments of the disclosure. [0009] Fig. 3C illustrates a 3D view of a device having an MTJ stack coupled to a positive spin Hall angle electrode with field assist, according to some embodiments of the disclosure.

[0010] Fig. 4 illustrates a cross-section of the positive spin Hall angle electrode with field assist, according to some embodiments of the disclosure.

[0011] Fig. 5 illustrates a cross-section of a die layout having the device of Fig. 3A formed in metal 3 (M3) and metal 2 (M2) layer regions, according to some embodiments of the disclosure.

[0012] Fig. 6 illustrates a cross-section of a die layout having the device of Fig. 3A formed in metal 2 (M2) and metal 1 (Ml) layer regions, according to some embodiments of the disclosure.

[0013] Fig. 7 illustrates a spin wave trans conductance scheme using the device of

Fig. 3A, according to some embodiments of the disclosure.

[0014] Fig. 8 illustrates a majority gate using the device of Fig. 3A, according to some embodiments of the disclosure.

[0015] Fig. 9 illustrates a plot showing improvement in energy-delay product using the device of Fig. 3A compared to the device of Fig. 1, in accordance with some

embodiments of the disclosure.

[0016] Fig. 10 illustrates a method flowchart of generating and detecting spin waves using positive spin Hall angle electrode with field assist, according to some embodiments of the disclosure.

[0017] Fig. 11 illustrates a smart device or a computer system or a SoC (System-on-

Chip) with device, spin wave transconductance scheme, and/or majority gate, according to some embodiments of the disclosure.

DETAILED DESCRIPTION

[0018] Some embodiments describe a spin Hall effect (SHE) MRAM with in-plane and/or out-of-plane magnetization. In some embodiments, SHE in combination of an Oersted field assist are applied via direct contact to a surface of a magnet to reduce the effective magnetic barrier of the magnet. In some embodiments, an electrode with positive spin Hall angle is used for the spin Hall and field assist to work in support of each other. In some embodiments, the positive spin Hall angle electrode comprises one of the following elements: Pt, Cu, Ir, or Mn. In some embodiments, the positive spin Hall angle electrode comprises at least one of the materials: Pt, CuPt, IrMn, Culr, or PtMn. In some embodiments, with a typical value of the spin Hall angle (e.g., 0.05 to 0.3), the contact Oersted field becomes significant to assist in the SHE switching. In some embodiments, both SHE and Oersted field operate in the same direction during the writing of the MRAM cells (e.g., memory bit-cells formed of magnetic junction).

[0019] There are many technical effects of the various embodiments. For example, in some embodiments, a perpendicular magnet switch is enabled using perpendicular magnet anisotropy (PMA) based magnetic devices (e.g., MRAM and logic) which comprises a switching mechanism based on spin orbit effects that generate perpendicular spin currents and Oersted field assist. The perpendicular magnet switch of some embodiments enables low programming voltages (or higher current for identical voltages) enabled by giant spin orbit effects (GSOE) for perpendicular magnetic memory and logic. The perpendicular magnet switch, of some embodiments, results in lower write error rates which enable faster MRAM (e.g., write time of less than 10 ns). The perpendicular magnet switch of some embodiments decouple write and read paths to enable faster read latencies. The perpendicular magnet switch of some embodiments uses significantly smaller read current through the MTJ and provides improved reliability of the tunneling oxide and MTJs. For example, less than 10 μΑ compared to 100 μΑ for nominal write is used by the perpendicular magnet switch of some embodiments. In some embodiments, the use of Oersted field allows the use of a low anisotropy effective field (Hk) magnets. For example, magnets with anisotropy field in the range of 50 to 500 Oe can be used that result in high density memory logic.

[0020] In the following description, numerous details are discussed to provide a more thorough explanation of embodiments of the present disclosure. It will be apparent, however, to one skilled in the art, that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.

[0021] Note that in the corresponding drawings of the embodiments, signals are represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme. [0022] Throughout the specification, and in the claims, the term "connected" means a direct connection, such as electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices. The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices. The term "circuit" or "module" may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on."

[0023] The term "scaling" generally refers to converting a design (schematic and layout) from one process technology to another process technology and subsequently being reduced in layout area. The term "scaling" generally also refers to downsizing layout and devices within the same technology node. The term "scaling" may also refer to adjusting (e.g., slowing down or speeding up - i.e. scaling down, or scaling up respectively) of a signal frequency relative to another parameter, for example, power supply level. The terms "substantially," "close," "approximately," "near," and "about," generally refer to being within +/- 10% of a target value.

[0024] Unless otherwise specified the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

[0025] For the purposes of the present disclosure, phrases "A and/or B" and "A or B" mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0026] The terms "left," "right," "front," "back," "top," "bottom," "over," "under," and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. For the purposes of present disclosure the terms "spin" and "magnetic moment" are used equivalently. More rigorously, the direction of the spin is opposite to that of the magnetic moment, and the charge of the particle is negative (such as in the case of electron).

[0027] Fig. 1 illustrates device 100 having an in-plane magnetic tunnel junction

(MTJ) stack coupled to a spin orbit coupling interconnect. Here, the stack of layers having MTJ 121 is coupled to an electrode 122 formed of spin Hall effect (SHE) or SOC material, where the SHE material converts charge current Iw (or write current) to spin polarized current Is. Device 100 forms a three terminal memory cell with SHE induced write mechanism and MTJ based read-out. Device 100 comprises MTJ 121, SHE Interconnect or electrode 122, and non-magnetic metal(s) 123a/b. In one example, MTJ 121 comprises layers 121a, 121b, and 121c. In some embodiments, layers 121a and 121c are ferromagnetic layers. In some embodiments, layer 121b is a metal or a tunneling dielectric. One or both ends along the horizontal direction of SHE Interconnect 122 is formed of non-magnetic metals 123a/b. Additional layers 121d, 121e, 121f, and 121g can also be stacked on top of layer 121c. In some embodiments, layer 121g is non-magnetic metal electrode.

[0028] A wide combination of materials can be used for material stacking of MTJ

121. For example, the stack of layers 121a, 121b, 121c, 121d, 121e, 121f, and 121g are formed of materials which include: Co _x FeyB _z , MgO, Co _x FeyB _z , Ru, Co _x FeyB _z , IrMn, and Ru, respectively, where 'x,' 'y,' and 'z' are fractions of elements in the alloys. Other materials may also be used to form MTJ 121. MTJ 121 stack comprises free magnetic layer 121a, MgO tunneling oxide 121b, a fixed magnetic layer 121c/d/e which is a combination of CoFe, Ru, and CoFe layers, respectively, referred to as Synthetic Anti-Ferromagnet (SAF), and an Anti-Ferromagnet (AFM) layer 121f. The SAF layer has the property, that the

magnetizations in the two CoFe layers are opposite, and allows for cancelling the dipole fields around the free magnetic layer such that a stray dipole field will not control the free magnetic layer.

[0029] In some embodiments, the free and fixed magnetic layers (121a and 121c, respectively) are formed of CFGG (i.e., Cobalt (Co), Iron (Fe), Germanium (Ge), or Gallium (Ga) or a combination of them). In some embodiments, FM 121a/c are formed from Heusler alloys. Heusler alloys are ferromagnetic metal alloys based on a Heusler phase. Heusler phases are intermetallic with certain composition and face-centered cubic crystal structure. The ferromagnetic property of the Heusler alloys are a result of a double-exchange mechanism between neighboring magnetic ions.

[0030] SHE Interconnect 122 (or the write electrode) include one or more of β-

Tantalum (β-Ta), Ta, β-Tungsten (β-W), W, Pt, Copper (Cu) doped with elements such as Iridium, Bismuth and any of the elements of 3d, 4d, 5d and 4f, 5f periodic groups in the Periodic Table which may exhibit high spin orbit coupling. SHE Interconnect 122 transitions into high conductivity non-magnetic metal(s) 123a/b to reduce the resistance of SHE Interconnect 122. The non-magnetic metal(s) 123a/b include one or more of: Cu, Co, a-Ta, Al, CuSi, or NiSi.

[0031] In one case, the magnetization direction of fixed magnetic layer 121c is perpendicular relative to the magnetization direction of free magnetic layer 121a (e.g., magnetization directions of the free and fixed magnetic layers are not parallel, rather they are orthogonal). For example, magnetization direction of free magnetic layer 121a is in-plane while the magnetization direction of fixed magnetic layer 121c is perpendicular to the in- plane. In another case, magnetization direction of fixed magnetic layer 121a is in-plane while the magnetization direction of free magnetic layer 121c is perpendicular to the in-plane.

[0032] The thickness of a ferromagnetic layer (e.g., fixed or free magnetic layer) may determine its equilibrium magnetization direction. For example, when the thickness of the ferromagnetic layer 121a/c is above a certain threshold (depending on the material of the magnet, e.g. approximately 1.5 nm for CoFe), then the ferromagnetic layer exhibits magnetization direction which is in-plane. Likewise, when the thickness of the ferromagnetic layer 121a/c is below a certain threshold (depending on the material of the magnet), then the ferromagnetic layer 121a/c exhibits magnetization direction which is perpendicular to the plane of the magnetic layer.

[0033] Other factors may also determine the direction of magnetization. For example, factors such as surface anisotropy (depending on the adjacent layers or a multi -layer composition of the ferromagnetic layer) and/or crystalline anisotropy (depending on stress and the crystal lattice structure modification such as FCC (face centered cubic lattice), BCC (body centered cubic lattice), or Llo-type of crystals, where Llo is a type of crystal class which exhibits perpendicular magnetizations), can also determine the direction of magnetization.

[0034] In this example, the applied current I _w is converted into spin current Is by SHE

Interconnect 122. This spin current switches the direction of magnetization of the free layer and thus changes the resistance of MTJ 121. However, to read out the state of MTJ 121, a sensing mechanism is needed to sense the resistance change.

[0035] The magnetic cell is written by applying a charge current via SHE

Interconnect 122. The direction of the magnetic writing (in free magnet layer 121a) is decided by the direction of the applied charge current. Positive currents (e.g., currents flowing in the +y direction) produce a spin injection current with transport direction (along the +z direction) and spins pointing to the +x direction. The injected spin current in turn produces spin torque to align the free magnet 121a (coupled to the SHE layer 122 of SHE material) in the +x direction. Negative currents (e.g., currents flowing in the -y direction) produce a spin injection current with transport direction (along the +z direction) and spins pointing to the -x direction. The injected spin current in-tum produces spin torque to align the free magnet 121a (coupled to the SHE material of layer 122) in the -x direction. In some embodiments, in materials with the opposite sign of the SHE/SOC effect, the directions of spin polarization and thus of the free layer magnetization alignment are reversed compared to the above.

[0036] Fig. 2A illustrates a cross-section view 200 of the spin orbit coupling interconnect with electrons having their spins polarized in-plane and deflected up and down resulting from a flow of charge current. It is pointed out that those elements of Fig. 2A having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. In this example, positive charge current represented by J _c produces spin-front (e.g., in the +x direction) polarized current 201 and spin-back (e.g., in the -x direction) polarized current 202. The injected spin current / _s generated by a charge current l _c in the write electrode 122 is given by:

T _s = P _SHE (w, t, _sf , e _SHE )(T _c Xz ) . . . (1) where, the vector of spin current / _s = / _† — /j, points in the direction of transferred magnetic moment and has the magnitude of the difference of currents with spin along and opposite to the spin polarization direction, z is the unit vector perpendicular to the interface, P _SHE is the spin Hall injection efficiency which is the ratio of magnitude of transverse spin current to lateral charge current, w is the width of the magnet, t is the thickness of the SHE

Interconnect 122, X _S f is the spin flip length in SHE Interconnect 122, Θ _5ΗΕ is the spin Hall angle for SHE Interconnect 122 to free ferromagnetic layer interface. The injected spin angular momentum responsible for the spin torque given by:

[0037] The generated spin up and down currents 201/202 (e.g., / _s ) are described as a vector cross-product given by:

[0038] This spin to charge conversion is based on Tunnel Magneto Resistance (TMR) which is highly limited in the signal strength generated. The TMR based spin to charge conversion has low efficiency (e.g., less than one). [0039] Since the spin polarization direction for the SOC materials of Figs. 1-2 are in- plane, a perpendicularly magnetized free magnet layer coupled to SOC interconnect 122 can be switched inefficiently and in the presence of a significant external magnetic field. This means forming devices (e.g., logic and memory) with perpendicular magnetic anisotropy (PMA) are a challenge with SOC interconnect 122. Here, perpendicularly magnetized free magnet refers to a magnet having magnetization which is perpendicular to the plane of the magnet as opposed to in-plane magnet that has magnetization in a direction along the plane of the magnet.

[0040] Fig. 2B illustrates plot 220 showing write energy-delay conditions for one transistor and one magnetic tunnel junction (MTJ) with SHE material compared to traditional MTJs. Here, x-axis is energy per write operation in femto-Joules (fJ) while the y-axis is delay in nano-seconds (ns).

[0041] Here, the energy-delay trajectory of SHE and MTJ devices are compared for in-plane magnet switching as the applied write voltage is varied. The energy-delay relationship (for in-plane switching) can be written as:

(τ + τ ₀ In (^r ) ² _{4 R} χ _M , π \ ,\

[0042] Where # _wr ; _te is the write resistance of the device (resistance of SHE electrode or resistance of MTJ-P or MTJ-AP, where MTJ-P is a MTJ with parallel magnetizations while MTJ-AP is an MTJ with anti-parallel magnetizations, μ ₀ is vacuum permeability, e is the electron charge. The equation shows that the energy at a given delay is directly proportional to the square of the Gilbert damping a. Here the characteristic time, τ ₀ =

as the spin polarization varies for various SHE metal electrodes (e.g., 223,

224, 225). Plot 220 shows five curves 221, 222, 223, 224, and 225. Curves 221 and 222 show write energy-delay conditions using traditional MTJ devices without SHE material.

[0043] For example, curve 221 shows the write energy-delay condition caused by switching a magnet from anti-parallel (AP) to parallel (P) state, while curve 222 shows the write energy-delay condition caused by switching a magnet from P to AP state. Curves 222, 223, and 224 show write energy-delay conditions of an MTJ with SHE material. Clearly, write energy-delay conditions of an MTJ with SHE material is much lower than write energy- delay conditions of an MTJ without SHE material. While write energy-delay of an MTJ with SHE material improves over a traditional MTJ without SHE material, further improvement in write energy-delay is desired. [0044] Fig. 2C illustrates plot 230 comparing reliable write times for spin Hall

MRAM and spin torque MRAMs. There are three cases considered in plot 230. Waveform 231 is the write time for in-plane MTJ, waveform 232 is the write time for PMA MTJ, and waveform 234 is the write time for spin Hall MTJ. All the cases considered in Fig. 2C assume a 30 X 60 nm magnet with 40 kT energy barrier and 3.5 nm SHE electrode thicknesses. The energy-delay trajectories of the devices are obtained assuming a voltage sweep from 0 V to 0.7 V in accordance to voltage restrictions of scaled CMOS. The energy- delay trajectory of the SHE-MTJ devices exhibits broadly two operating regions A) Region 1

M Ve

where the energy-delay product is approximately constant (τ _α < ^s /j μ _β )' B) Region 2

M Ve

where the energy is proportional to the delay τ _α > ^s /j p The two regions are separated by energy minima at τ _ορί = ^ ^s ^ ^e j ^ ^ where minimum switching energy is obtained for the spin torque devices.

[0045] The energy-delay trajectory of the STT-MTJ devices is limited with a minimum delay of 1 ns for in-plane devices at 0.7 V maximum applied voltage, the switching energy for P-AP and AP-P are in the range of 1 pJ/write. In contrast, the energy-delay trajectory of SHE-MTJ (in-plane anisotropy) devices can enable switching times as low as 20 ps (β-W with 0.7 V, 20 fj/bit) or switching energy as small as 2 fj (β-W with 0.1 V, 1.5 ns switching time).

[0046] Fig. 3A illustrates a 3D view of a device 300 having an MTJ stack coupled to a positive spin Hall angle electrode with field assist, according to some embodiments of the disclosure. Fig. 3B illustrates a top view 320 of the device of Fig. 3A, according to some embodiments of the disclosure. It is pointed out that those elements of Figs. 3A-B having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0047] Device 300 comprises a magnetic junction (e.g., MTJ 321 or a spin valve) which couples to an electrode 322 exhibiting spin orbit effects and Oersted field assist. Other materials and layers are similar as those of device 100. For example, the SAF, AFM, and metal interconnects 123 are the same as those described with reference to 100 of Fig. 1. Referring back to Fig. 3A, device 300 illustrates a geometry of a 3-terminal memory cell with a positive spin Hall angle electrode 322 exhibiting spin orbit effects and Oersted field assist. In some embodiments, the positive spin Hall angle electrode 322 exhibiting spin orbit effects and Oersted field assist provides a write mechanism while the PMA based MTJ provides the read-output mechanism.

[0048] In some embodiments, MTJ 321 comprises free perpendicular magnet layer

(FMl) 321a, layer 121b (e.g., MgO tunneling oxide for MTJ, or metal layer for spin valve), a fixed perpendicular magnet (FM2) 121c with Synthetic Anti-Ferro-magnet (SAF) 121d and 121e- CoFe/Ru based, and Anti-Ferromagnet (AFM) 121f. The SAF layer 121d/e allows for cancelling the dipole fields around the free layer. The magnets of various embodiments can be ferromagnets or paramagnets.

[0049] In some embodiments, positive spin Hall angle electrode 322 exhibiting spin orbit effects comprises a material which includes one of: Mn, Pt, Ir, or Cu. Here the term "positive spin Hall angle" (or +9SHE) generally refers to the case in which the vectors J _c , z , andJs in Eq. (3) form a right triple. In some embodiments, when charge current flows through electrode 322, Oersted field is generated which assists in switching magnetization of layer 321a. In some embodiments, the positive spin Hall angle electrode 322 comprises a material which is one of CtPt, Culr, IrMn, or PtMn. This material allows for Oersted field to be generated when charge current flows through such material. The Oersted field is an assist field which assists in switching of magnetization of layer 321a which is already under stress by spin torque, in accordance with some embodiments. The switching allows for changing the memory state of the device having MTJ 321 and positive spin Hall angle electrode 322, in accordance with some embodiments.

[0050] The combination of materials for electrode 322 which allows the usage of

Oersted field also results in usage of low Hk magnet for layer 321a. Here, low Hk refers to an anisotropy field of a magnet in the range of 50 Oe to 500 Oe, while high Hk refers to an anisotropy field of a magnet of 500 Oe and higher.

[0051] In some embodiments, the free perpendicular magnet layer 321a of the magnetic junction (e.g., spin valve or MTJ 321), which is coupled to interface normal spin orbit material based interconnect 322, comprises one or a combination of materials which include one or more of: a Heusler alloy, Co, Fe, Ni, Gd, B, Ge, Ga, permalloy, or Yttrium Iron Gamet (YIG). In some embodiments, the Heusler alloy is a material which includes one or more of: Cu ₂ MnAl, Cu ₂ MnIn, Cu ₂ MnSn, Ni ₂ MnAl, Ni ₂ MnIn, Ni ₂ MnSn, Ni ₂ MnSb, Ni ₂ MnGa Co ₂ MnAl, Co ₂ MnSi, Co ₂ MnGa, Co ₂ MnGe, Pd ₂ MnAl, Pd ₂ MnIn, Pd ₂ MnSn, Pd ₂ MnSb, Co ₂ FeSi, Co ₂ FeAl, Fe ₂ VAl, Mn ₂ VGa, Co ₂ FeGe, MnGa, or MnGaRu. [0052] In some embodiments, the free perpendicular magnet layer 321a of the magnetic junction (e.g., spin valve or MTJ 321) is formed of a stack of materials, wherein the materials for the stack include one or more of: Co and Pt; Co and Pd; Co and Ni; MgO, CoFeB, Ta, CoFeB, and MgO; MgO, CoFeB, W, CoFeB, and MgO; MgO, CoFeB, V, CoFeB, and MgO; MgO, CoFeB, Mo, CoFeB, and MgO; Mn _x Ga _y ; Materials with Llo symmetry; or materials with tetragonal crystal structure.

[0053] Llo is a crystallographic derivative structure of a FCC structure and has two of the faces occupied by one type of atom and the corner and the other face occupied with the second type of atom. When phases with the Llo structure are ferromagnetic the

magnetization vector usually is along the [0 0 1] axis of the crystal. Examples of materials with Llo symmetry include CoPt and FePt. Examples of materials with tetragonal crystal structure and magnetic moment are Heusler alloys such as CoFeAl, MnGe, MnGeGa, and MnGa. In some embodiments, the free magnet layer of the magnetic junction (e.g., spin valve or MTJ 321) is formed of a single layer of one or more materials. In some

embodiments, the single layer is formed of MnGa.

[0054] In some embodiments, the fixed perpendicular magnet layer 121c is formed with interfacial PMA (perpendicular magnetic anisotropy), multi-interface PMA, magnetic crystalline anisotropy or multi-layer PMA. In some embodiments, the free perpendicular magnet layer 121a is formed with interfacial PMA, multi-interface PMA, magnetic crystalline anisotropy or multi-layer PMA. In some embodiments, TMR (tunnel magneto resistance) is used for memory readout from PMA-MTJ 321. In some embodiments, the magnet with PMA is formed of a stack of materials, wherein the materials for the stack include one or more of: Co and Pt; Co and Pd; Co and Ni; MgO, CoFeB, Ta, CoFeB, and MgO; MgO, CoFeB, W, CoFeB, and MgO; MgO, CoFeB, V, CoFeB, and MgO; MgO, CoFeB, Mo, CoFeB, and MgO; Mn _x Ga _y ; Materials with Llo symmetry; or materials with tetragonal crystal structure. In some embodiments, the magnet with PMA is formed of a single layer of one or more materials. In some embodiments, the single layer comprises Mn and Ga. For example, the signal layer comprises MnGa.

[0055] In some embodiments, the perpendicular magnets of layer 321a of the magnetic junction (e.g., spin valve or MTJ 321) are formed with a sufficiently high anisotropy (indicated by an anisotropy effective field Hk) and sufficiently low saturated magnetization (M _s ) to increase injection of spin currents. Saturated magnetization M _s is generally the state reached when an increase in applied external magnetic field H cannot increase the magnetization of the material. Here, sufficiently low M _s refers to M _s less than 200 kA/m (kilo- Amperes per meter). Anisotropy Hk generally refers to the material property which is directionally dependent. Materials with high Hk are materials with material properties that are highly directionally dependent. Here, sufficiently high Hk in context of Heusler alloys is considered to be greater than 2000 Oe (Oersted).

[0056] The magnetic cell is written by applying a charge current via the AFM interconnect 322 (or electrode). The charge current through electrode 322 causes an Oersted field to be generated that assists in switching of free magnet layer 321a with PMA to another phase. For example, the Oersted field reduces the effective magnetic barrier of free magnet layer 321a. The direction of the magnetic writing is decided by the direction of the applied charge current. Positive currents (along +y) produce a spin injection current with transport direction (along +z) and spins pointing to (+z) direction. Negative currents (along -y direction) produce a spin injection current with transport direction (along +z direction) and spins pointing to (-z) direction. The direction of the Oersted field also switches according to the direction of flow of current. For example, when positive current flows through electrode 322, the Oersted field is clockwise along electrode 322, and when negative current flows through electrode 322, the Oersted field is counter clockwise along electrode 322.

[0057] Fig. 3C illustrates plot 330 showing thickness of free magnet layer 321a and corresponding anisotropy effective field. Two saturation regions 331 and 332 are shown. The high anisotropy effective field region (e.g., region 331) is generally achieved for thicker magnets while low saturation region (e.g., region 332) is achieved for thinner magnets. In various embodiments, free magnet layer 321a resulting in low Hk (region 322) is used for forming device 300 which allows for high volume manufacturing device 300. For example, smaller (or thinner) magnets can be used resulting in smaller device size for device 300. As such, memories with such devices can be made smaller in size (e.g., memories with higher density and smaller size). The two lines in plot 330 are for two different magnet sizes (e.g., 120 nm x 60 nm, and 100 nm x 50 nm).

[0058] Fig. 3D illustrates a 3D view of device 340 having an MTJ stack coupled to a positive spin Hall angle electrode with field assist, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 3D having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. Here, device 340 is same as device 300 except that current Iw flows along -y direction. As such, the Oersted assist field is in opposite direction compared to the Oersted assist field shown for Fig. 3A. In this case, the magnetization after switching of magnet 321a is also 180 degrees opposite to that of magnetization of magnet 321a of Fig. 3D.

[0059] Fig. 4 illustrates a cross-section 400 of the positive spin Hall angle electrode with field assist, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 4 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0060] In this example, positive charge current (e.g., current in the +x direction) represented by Jc produces spin-up (e.g., in the z+ direction) polarized current 401 and spin- down (e.g., in the -z direction) polarized current 402 in the direction normal to interconnect 322. The generated current is expressed as a tensor product instead of a cross product:

Js ⁼ Qyzz-RBE-Jc ^a zz

where ] _s is the density of the spin current 401/402 polarized along the z-axis and propagating along z-axis, 0 _YZZ _ _RBE is the effective Rashba-Bychkov effect ratio relating the spin polarized current density with the charge current density along the 'y' direction, and ] _c is the charge current density.

[0061] The injected spin current / _s in turn produces spin torque to align the free perpendicular magnet in substantially +z or -z direction. In some embodiments, an auxiliary factor for aligning the free perpendicular magnet in substantially +z or -z direction is Oersted field assist from positive spin Hall angle electrode 322 which produces an additional torque which is non-zero even if it is aligned to the direction of the spin polarized current.

[0062] In some embodiments, Oersted field 403 is generated from positive spin Hall angle electrode 322 which assists with switching of free perpendicular magnet 321a when charge current flows through electrode 322. The direction of switching of the magnetization depends on the direction of spin polarization.

[0063] The transverse spin current (/ _s = It — with spin direction cQ ) for a charge current I _c in the write electrode 322 is given by:

= PRBE ( ^w < t> f> Qyzz-RBE) (. ^{A X} )

where P _RBE = (/†— /j, )/( /† + /j, ) is the Rashba Bychkov effect injection efficiency which is the ratio of magnitude of transverse spin current to lateral charge current, w is the width of the magnet, t is the thickness of the Interconnect 322, X _S f is the spin flip length in Interconnect 322, 9 _yzz _ _RBE is the Rashba-Bychkov effect ratio for Interconnect 322 to free magnetic layer interface. The injected spin torque is given by:

[0064] Various embodiments describe a highly efficient transduction method and associated apparatus for converting spin currents to charge currents. In some embodiments, spin-to-charge conversion is achieved via spin orbit interaction in positive spin Hall angle electrode 322 in metallic interfaces (e.g., using Inverse Rashba-Bychkov Effect) where a spin current injected from an input magnet produces a charge current. Table 1 summarizes transduction mechanisms for converting spin current to charge current and charge current to spin current for bulk materials and interfaces.

Table 1: Transduction mechanisms for Spin to Charge and Charge to Spin Conversion due to Spin-Orbit

Coupling

[0065] While the various embodiments are described here with reference to free magnet 321a having PMA, the embodiments of various embodiments also apply to in-plane magnets. For example, the Oersted field generated from charge current flow through electrode 322 can also assist with switching magnetization of in-plane magnet. The direction of magnetization of the in-plane magnet depends on the direction of spin polarization from electrode 322.

[0066] Fig. 5 illustrates a cross-section 500 of a die layout having the device of Fig.

3A formed in metal 3 (M3) and metal 2 (M2) layer regions, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 5 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0067] Cross-section 500 illustrates an active region having a transistor MN comprising diffusion region 501, a gate terminal 502, drain terminal 504, and source terminal 503. The source terminal 503 is coupled to SL (source line) via poly or via, where the SL is formed on Metal 0 (M0). In some embodiments, the drain terminal 504 is coupled to MOa (also metal 0) through via 505. The drain terminal 504 is coupled to positive spin Hall angle electrode 322 with field assist through Via 0-1 (e.g., via connecting metal 0 to metal 1 layers), metal 1 (Ml), Via 1 -2 (e.g., via connecting metal 1 to metal 2 layers), and Metal 2 (M2). In some embodiments, the magnetic junction (e.g., MTJ 321 or spin valve) is formed in the metal 3 (M3) region. In some embodiments, the perpendicular free magnet layer of the magnetic junction (MTJ 321 or spin valve) couples to positive spin Hall angle electrode 322 with field assist. In some embodiments, the fixed magnet layer of magnetic junction couples to the bit-line (BL) via positive spin Hall angle electrode 322 with field assist through Via 3-4 (e.g., via connecting metal 4 region to metal 4 (M4)). In this example, bit-line is formed on M4.

[0068] In some embodiments, n-type transistor MN is formed in the frontend of the die while the positive spin Hall angle electrode 322 with field assist is located in the backend of the die. Here, the term "backend" generally refers to a section of a die which is opposite of a "frontend" and where an IC (integrated circuit) package couples to IC die bumps. For example, high level metal layers (e.g., metal layer 6 and above in a ten metal stack die) and corresponding vias that are closer to a die package are considered part of the backend of the die. Conversely, the term "frontend" generally refers to a section of the die that includes the active region (e.g., where transistors are fabricated) and low level metal layers and corresponding vias that are closer to the active region (e.g., metal layer 5 and below in the ten metal stack die example).

[0069] In some embodiments, the positive spin Hall angle electrode 322 with field assist is located in the backend metal layers or via layers for example in Via 3. In some embodiments, the electrical connectivity to the device is obtained in layers M0 and M4 or Ml and M5 or any set of two parallel interconnects.

[0070] Fig. 6 illustrates cross-section 600 of a die layout having the device of Fig. 3A formed in metal 2 and metal 1 layer regions, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 6 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. Compared to Fig. 5, here the magnetic junction (e.g., MTJ 321 or spin valve) is formed in the metal 2 region and/or Via 1 -2 region. In some embodiments, the positive spin Hall angle electrode 322 with field assist is formed in the metal 1 region.

[0071] Fig. 7 illustrates a spin wave trans conductance scheme 700 using the device of

Fig. 3A, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 7 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0072] In some embodiments, scheme 700 comprises an input positive spin Hall angle electrode 723 with field assist (or SOC layer 732), spin wave interconnect 731, and output positive spin Hall angle electrode 733 with field assist (or layer exhibiting inverse SOC effect also referred to as ISOC 733). In some embodiments, SOC layer 732 is coupled to a spin wave generator (e.g., current source 704) which has its terminals coupled to two opposite ends of SOC 732. In some embodiments, the spin wave generator comprises at least one of: current source, an antenna, TMR device, or a magnetoelectric device.

[0073] In some embodiments, ISOC (inverse spin orbit coupling) layer 733 is coupled to a spin wave detector (e.g., voltage detector 705) which has its terminals coupled to two opposite ends of ISOC 733. In some embodiments, both SOC 732 and ISOC 733 are positive spin Hall angle electrodes with field assist. In some embodiments, one end of spin wave interconnect 731 is coupled to middle region of SOC 732. In some embodiments, the other end of spin wave interconnect 731 is coupled to a middle region of ISOC 733.

[0074] In some embodiments, positive spin Hall angle electrode 732 with field assist comprises layers which are the same as those described with reference to interconnect 322. In some embodiments, positive spin Hall angle electrode 733 with field assist comprises of materials exhibiting inverse spin orbit coupling (ISOC) such as one of inverse SHE (ISHE) or inverse Rashba-Bychkov effect (IRBE). In some embodiments, SOC layer 732 and ISOC layer 733 are formed of the same material, but exhibit different functions. For example, SOC layer 732 converts charge current from IAC 704 into perpendicular spin currents (e.g., perpendicular to the plane of spin wave interconnect 731). In some embodiments, spin wave generator 704 can be a current source, an antenna, or any other suitable device.

[0075] In some embodiments, spin wave interconnect 731 is a ferromagnet (FM). In some embodiments, FM 731 has perpendicular magnetic anisotropy. In some embodiments, FM 731 is formed of the same materials as the free perpendicular magnet of MTJ 321.

[0076] In some embodiments, the current through SOC layer 732 generates spin currents pointing perpendicular to the plan of SOC layer 732. These spin currents cause spin waves (or domain walls) to be generated in FM 731. The spin waves propagate along the length of FM 731 towards the other end of FM 731. At the other end of FM 731, the spin wave is converted into charge current by inverse Rashba-Bychkov effect of ISOC layer 733. This charge current causes a potential difference between the two ends of ISOC layer 733. The potential difference is detected by a spin wave detector (e.g., voltage source 705). [0077] Fig. 8 illustrates majority gate 800 using the device of Fig. 3A, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 8 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0078] In some embodiments, multiple domain walls or spin waves are generated by different spin wave generating sources, and these spin waves interact with one another to generate a resultant spin wave. This resultant spin wave is a function of the majority of the spin waves, in accordance with some embodiments. The resultant spin wave is then converted into charge current and detected by a spin wave detector.

[0079] Majority gate 800 illustrates three inputs (however, the embodiments can be expanded to any odd number of inputs greater than three). These three inputs are SOC 822a coupled to a spin wave generator 804a, SOC 822b coupled to a spin wave generator 804b, and SOC 822c coupled to a spin wave generator 804c. In some embodiments, SOC 822a is coupled to FM based spin wave interconnect 823a (or simply FM 823a). In some embodiments, SOC 822b is coupled to FM based spin wave interconnect 823b (or simply FM 823b). In some embodiments, SOC 822c is coupled to FM based spin wave interconnect 823c (or simply FM 823c). In some embodiments, spin wave interconnects 823a, 823b, and 823c form a 'T' junction. In some embodiments, spin wave interconnects 823a, 823b, and 823c form a 'Y' junction. In some embodiments, the junction point is coupled to another FM spin wave interconnect 823d (or simply FM 823d). In some embodiments, FM 823d is coupled to ISOC 824 which is coupled to a spin wave detector 805.

[0080] As described with reference to Fig. 7, here spin waves (or domain walls) are generated in a similar way by each SOC layer using Rashba-Bychkov effect. As such, three spin waves are generated in this example that interact at the junction (e.g., 'T' junction or 'Y' junction). At the junction, a resultant spin wave is generated which takes the phase of magnetization precession pertinent to the majority of the input spin waves. The resultant spin wave travels on FM 823d and is converted into charge by ISOC 824 using inverse Rashba- Bychkov effect. The charge current generated by inverse Rashba-Bychkov effect is then detected as a potential difference between the two ends of ISOC 824, in accordance with some embodiments. In various embodiments, the SOC and ISOC layers comprise the same materials as positive spin Hall angle electrode 322 with field assist.

[0081] Fig. 9 illustrates plot 900 showing improvement in energy-delay product using the device of Fig. 3A compared to the device of Fig. 1, in accordance with some

embodiments of the disclosure. It is pointed out that those elements of Fig. 9 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. Here, x-axis is Write Energy (in fj) and y-axis is Delay (in ns). Here, two the energy-delay trajectories are compared as write voltage is varied— 901 which is the energy-delay trajectory of device 100 and 902 is the energy delay trajectory of device 300. Plot 900 illustrates that device 300 provides a shorter (i.e., improved) energy-delay product than device 100.

[0082] Fig. 10 illustrates a method flowchart 1000 of generating and detecting spin waves using positive spin Hall angle electrode with field assist, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 10 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0083] Although the blocks in the flowchart with reference to Fig. 10 are shown in a particular order, the order of the actions can be modified. Thus, the illustrated embodiments can be performed in a different order, and some actions/blocks may be performed in parallel. Some of the blocks and/or operations listed in Fig. 10 are optional in accordance with certain embodiments. The numbering of the blocks presented is for the sake of clarity and is not intended to prescribe an order of operations in which the various blocks must occur.

Additionally, operations from the various flows may be utilized in a variety of combinations.

[0084] At block 1001, a charge current is passed through positive spin Hall angle electrode with field assist (e.g., SOC 732 and SOC 822a). For example, charge current from IAC 704 or IAC 804 is passed through SOC 732 and SOC 822a, respectively. In some embodiments, the positive spin Hall angle electrode with field assist generates spin currents perpendicular to its plane. At block 1002, a first spin wave is generated by positive spin Hall angle electrode (e.g., SOC 732 and SOC 822a), where the first spin wave is to propagate through a first FM adjacent to the positive spin Hall angle electrode with field assist at one end of the first FM (e.g., spin wave interconnect FM 721 and spin wave interconnect FM 823a).

[0085] At block 1003, a voltage detector is applied across two ends along a length of the positive spin Hall angle electrode with field assist (e.g., ISOC 733 and ISOC 824). For example, voltage detector VDC 705 is applied across ISOC 833 layer to detect the charge generated by ISOC 733. At block 1004, a voltage across positive spin Hall angle electrode with field assist, the positive spin Hall angle electrode with field assist being adjacent to the first FM at another end of the first FM, wherein the voltage is according to the generated first spin wave. [0086] In some embodiments, the method further comprises generating a second spin wave which propagates through a second FM, wherein the second FM is adjacent to the positive spin Hall angle electrode (that provides inverse SOC) at one end of the second FM. In some embodiments, the method comprises generating a third spin wave which propagates through a third FM, wherein the third FM is adjacent to the positive spin Hall angle electrode with field assist (that provides inverse SOC) at one end of the third FM. In some embodiments, detecting the voltage across the positive spin Hall angle electrode with field assist comprises: applying a voltage detector across two ends along a length of the positive spin Hall angle electrode with field assist, and determining a logic value which is according to the voltage and the first, second, and third spin waves.

[0087] Fig. 11 illustrates a smart device or a computer system or a SoC (System-on-

Chip) 1600 with device 300, spin wave trans conductance scheme 700, and/or majority gate 800, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 11 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0088] For purposes of the embodiments, the transistors in various circuits and logic blocks described here are metal oxide semiconductor (MOS) transistors or their derivatives, where the MOS transistors include drain, source, gate, and bulk terminals. The transistors and/or the MOS transistor derivatives also include Tri-Gate and FinFET transistors, Gate All Around Cylindrical Transistors, Tunneling FET (TFET), Square Wire, or Rectangular Ribbon Transistors, ferroelectric FET (FeFETs), or other devices implementing transistor functionality like carbon nanotubes or spintronic devices. MOSFET symmetrical source and drain terminals i.e., are identical terminals and are interchangeably used here. A TFET device, on the other hand, has asymmetric Source and Drain terminals. Those skilled in the art will appreciate that other transistors, for example, Bi-polar junction transistors (BJT PNP/NPN), BiCMOS, CMOS, etc., may be used without departing from the scope of the disclosure.

[0089] Fig. 11 illustrates a block diagram of an embodiment of a mobile device in which flat surface interface connectors could be used. In some embodiments, computing device 1600 represents a mobile computing device, such as a computing tablet, a mobile phone or smart-phone, a wireless-enabled e-reader, or other wireless mobile device. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device 1600. [0090] In some embodiments, computing device 1600 includes first processor 1610 with device 300, spin wave transconductance scheme 700, and/or majority gate 800, according to some embodiments discussed. Other blocks of the computing device 1600 may also include device 300, spin wave transconductance scheme 700, and/or maj ority gate 800, according to some embodiments. The various embodiments of the present disclosure may also comprise a network interface within 1670 such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant.

[0091] In some embodiments, processor 1610 (and/or processor 1690) can include one or more physical devices, such as microprocessors, application processors,

microcontrollers, programmable logic devices, or other processing means. The processing operations performed by processor 1610 include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing device 1600 to another device. The processing operations may also include operations related to audio I/O and/or display I/O.

[0092] In some embodiments, computing device 1600 includes audio subsystem

1620, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device 1600, or connected to the computing device 1600. In one embodiment, a user interacts with the computing device 1600 by providing audio commands that are received and processed by processor 1610.

[0093] In some embodiments, computing device 1600 comprises display subsystem

1630. Display subsystem 1630 represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device 1600. Display subsystem 1630 includes display interface 1632, which includes the particular screen or hardware device used to provide a display to a user. In one embodiment, display interface 1632 includes logic separate from processor 1610 to perform at least some processing related to the display. In one embodiment, display subsystem 1630 includes a touch screen (or touch pad) device that provides both output and input to a user. [0094] In some embodiments, computing device 1600 comprises I/O controller 1640.

I/O controller 1640 represents hardware devices and software components related to interaction with a user. I/O controller 1640 is operable to manage hardware that is part of audio subsystem 1620 and/or display subsystem 1630. Additionally, I/O controller 1640 illustrates a connection point for additional devices that connect to computing device 1600 through which a user might interact with the system. For example, devices that can be attached to the computing device 1600 might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.

[0095] As mentioned above, I/O controller 1640 can interact with audio subsystem

1620 and/or display subsystem 1630. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device 1600. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem 1630 includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I/O controller 1640. There can also be additional buttons or switches on the computing device 1600 to provide I/O functions managed by I/O controller 1640.

[0096] In some embodiments, I/O controller 1640 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in the computing device 1600. The input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).

[0097] In some embodiments, computing device 1600 includes power management

1650 that manages battery power usage, charging of the battery, and features related to power saving operation. Memory subsystem 1660 includes memory devices for storing information in computing device 1600. Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory subsystem 1660 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device 1600.

[0098] Elements of embodiments are also provided as a machine-readable medium

(e.g., memory 1660) for storing the computer-executable instructions (e.g., instructions to implement any other processes discussed herein). The machine-readable medium (e.g., memory 1660) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer- executable instructions. For example, embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).

[0099] In some embodiments, computing device 1600 comprises connectivity 1670.

Connectivity 1670 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device 1600 to communicate with external devices. The computing device 1600 could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.

[00100] Connectivity 1670 can include multiple different types of connectivity. To generalize, the computing device 1600 is illustrated with cellular connectivity 1672 and wireless connectivity 1674. Cellular connectivity 1672 refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards. Wireless connectivity (or wireless interface) 1674 refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication.

[00101] In some embodiments, computing device 1600 comprises peripheral connections 1680. Peripheral connections 1680 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that the computing device 1600 could both be a peripheral device ("to" 1682) to other computing devices, as well as have peripheral devices ("from" 1684) connected to it. The computing device 1600 commonly has a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device 1600. Additionally, a docking connector can allow computing device 1600 to connect to certain peripherals that allow the computing device 1600 to control content output, for example, to audiovisual or other systems.

[00102] In addition to a proprietary docking connector or other proprietary connection hardware, the computing device 1600 can make peripheral connections 1680 via common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.

[00103] Reference in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of "an embodiment," "one embodiment," or "some embodiments" are not necessarily all referring to the same embodiments. If the specification states a component, feature, structure, or characteristic "may," "might," or "could" be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to "a" or "an" element, that does not mean there is only one of the elements. If the specification or claims refer to "an additional" element, that does not preclude there being more than one of the additional element.

[00104] Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[00105] While the disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. The embodiments of the disclosure are intended to embrace all such alternatives, modifications, and variations as to fall within the broad scope of the appended claims.

[00106] In addition, well known power/ground connections to integrated circuit (IC) chips and other components may or may not be shown within the presented figures, for simplicity of illustration and discussion, and so as not to obscure the disclosure. Further, arrangements may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present disclosure is to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.

[00107] The following examples pertain to further embodiments. Specifics in the examples may be used anywhere in one or more embodiments. All optional features of the apparatus described herein may also be implemented with respect to a method or process.

[00108] Example 1 is an apparatus which comprises: a magnetic junction having a first layer, wherein the first layer includes free magnetic material; and an interconnect adjacent to the first layer, wherein the interconnect comprises a material including one or more of Cu, Ir, or Mn.

[00109] Example 2 includes all features of example 1, wherein the material to provide a positive spin Hall angle.

[00110] Example 3 includes all features of example 1, wherein the material includes one of: CuPt, IrMn, Culr, or PtMn.

[00111] Example 4 is according to any one of examples 1 to 3, wherein the first layer comprises a material having anisotropy effective field Hk in a range of 50 Oe to 500 Oe.

[00112] Example 5 is according to any one of examples 1 to 4, wherein the first layer has perpendicular magnetic anisotropy (PMA) such that the first layer has anisotropy axis perpendicular to a plane of a device.

[00113] Example 6 according to any of the preceding claims, wherein the interconnect is to generate a magnetic field to assist switching of magnetization of the first layer.

[00114] Example 7 includes all features of example 6, wherein the interconnect is to generate spin Hall effect (SHE).

[00115] Example 8 is according to any of the preceding claims, wherein the magnetic junction is one of a spin valve or a magnetic tunneling junction (MTJ).

[00116] Example 9 is according to any of the preceding claims, wherein the first layer comprises one or a combination of materials which include one of: a Heusler alloy, Co, Fe, Ni, Gd, B, Ge, Ga, permalloy, or Yttrium Iron Garnet (YIG).

[00117] Example 10 includes all features of example 9, wherein the Heusler alloy includes one of: Cu ₂ MnAl, Cu ₂ MnIn, Cu ₂ MnSn, Ni ₂ MnAl, Ni ₂ MnIn, Ni ₂ MnSn, Ni ₂ MnSb, Ni ₂ MnGa Co ₂ MnAl, Co ₂ MnSi, Co ₂ MnGa, Co ₂ MnGe, Pd ₂ MnAl, Pd ₂ MnIn, Pd ₂ MnSn, Pd ₂ MnSb, Co ₂ FeSi, Co ₂ FeAl, Fe ₂ VAl, Mn ₂ VGa, Co ₂ FeGe, MnGa, or MnGaRu.

[00118] Example 11 includes all features of example 9, wherein the Heusler alloy includes one or more of Co, Cu, Fe, Ga, Ge, In, Mn, Al, In, Sb, Si, Sn, Ni, Pd, Ru, or V.

[00119] Example 12 is according to any of examples 1 to 8, wherein the first layer comprises a stack of materials, wherein the materials for the stack include one of: Co and Pt; Co and Pd; Co and Ni; MgO, CoFeB, Ta, CoFeB, and MgO; MgO, CoFeB, W, CoFeB, and MgO; MgO, CoFeB, V, CoFeB, and MgO; MgO, CoFeB, Mo, CoFeB, and MgO; or Mn _x Ga _y .

[00120] Example 13 is according to any of examples 1 to 8, wherein the first layer comprises a single layer of one or more materials.

[00121] Example 14 includes all features of example 13, wherein the single layer includes: Mn and Ga.

[00122] Example 15 is an apparatus which comprises: a magnetic junction having a first layer, the first layer including free magnetic material; and a second layer comprising a material including one or more of Cu, Ir, or Mn, the second layer being adjacent to one end of the first layer.

[00123] Example 16 includes all features of example 15, wherein the material is to provide a positive spin Hall angle.

[00124] Example 17 is according to any of examples 15 to 16, wherein the material of the second layer is to provide field assist in conjunction with spin orbit coupling to the first layer.

[00125] Example 18 is according to any of examples 15 to 16, wherein the material of the second layer includes one of: CuPt, IrMn, Culr, or PtMn.

[00126] Example 19 is according to any of examples 15 to 16, wherein the free magnetic material comprises a material having anisotropy effective field Hk in a range of 50 Oe to 500 Oe.

[00127] Example 20 is according to any of examples 15 to 16 comprises a spin wave generator adjacent to the second layer.

[00128] Example 21 includes features of example 20, wherein the spin wave generator comprises at least one of: an antenna, a tunneling magnetoresistance (TMR) device, or a magnetoelectric device.

[00129] Example 22 is according to any of claims 20 to 21 comprises a spin wave detector adjacent to another end of the first layer. [00130] Example 23 includes features of example 15, wherein the first layer comprises one or a combination of materials which include one of: a Heusler alloy, Co, Fe, Ni, Gd, B, Ge, Ga, permalloy, or Yttrium Iron Garnet (YIG).

[00131] Example 24 includes features of example 23, wherein the Heusler alloy is a material which includes one of: Cu ₂ MnAl, Cu ₂ MnIn, Cu ₂ MnSn, Ni ₂ MnAl, Ni ₂ MnIn, Ni ₂ MnSn, Ni ₂ MnSb, Ni ₂ MnGa Co ₂ MnAl, Co ₂ MnSi, Co ₂ MnGa, Co ₂ MnGe, Pd ₂ MnAl, Pd ₂ MnIn, PdJVInSn, Pd ₂ MnSb, Co ₂ FeSi, Co ₂ FeAl, Fe ₂ VAl, Mn ₂ VGa, Co ₂ FeGe, MnGa, or MnGaRu.

[00132] Example 25 includes features of example 15, wherein the first layer comprises a stack of materials, and wherein the materials for the stack include one of: Co and Pt; Co and Pd; Co and Ni; MgO, CoFeB, Ta, CoFeB, and MgO; MgO, CoFeB, W, CoFeB, and MgO; MgO, CoFeB, V, CoFeB, and MgO; MgO, CoFeB, Mo, CoFeB, and MgO; or Mn _x Ga _y .

[00133] Example 26 includes features of example 15, wherein the first layer comprises a single layer of one or more materials.

[00134] Example 27 includes features of example 26, wherein the single layer includes: Mn and Ga.

[00135] Example 28 is a system which comprises: a memory; a processor coupled to the memory, the processor having a spin wave switch, which comprises an apparatus according to any one of examples 1 to 14; and a wireless interface to allow the processor to communicate with another device.

[00136] Example 29 is a system which comprises: a memory; a processor coupled to the memory, the processor having an apparatus according to any one of examples 15 to 27; and a wireless interface to allow the processor to communicate with another device.

[00137] Example 30 is a method which comprises: forming a magnetic junction having a first layer, wherein the first layer includes free magnetic material; and forming an interconnect adjacent to the first layer, wherein the interconnect comprises a material including one or more of Cu, Ir, or Mn.

[00138] Example 31 includes all features of example 30, wherein the material to provide a positive spin Hall angle.

[00139] Example 32 includes all features of example 30, wherein the material includes one of: CuPt, IrMn, Culr, or PtMn.

[00140] Example 33 is according to any one of examples 30 to 32, wherein the first layer comprises a material having anisotropy effective field Hk in a range of 50 Oe to 500 Oe. [00141] Example 34 according to any one of examples 30 to 33, wherein the first layer has perpendicular magnetic anisotropy (PMA) such that the first layer has anisotropy axis perpendicular to a plane of a device.

[00142] Example 35 according to any one of examples 30 to 34 comprises generating a magnetic field to assist switching of magnetization of the first layer.

[00143] Example 36 according to any one of examples 30 to 34 comprises generating spin Hall effect (SHE).

[00144] Example 37 is according to any one of examples 30 to 34, wherein the magnetic junction is one of a spin valve or a magnetic tunneling junction (MTJ).

[00145] Example 38 is according to any one of examples 30 to 34, wherein the first layer comprises one or a combination of materials which include one of: a Heusler alloy, Co, Fe, Ni, Gd, B, Ge, Ga, permalloy, or Yttrium Iron Garnet (YIG).

[00146] Example 39 includes all features of example 38, wherein the Heusler alloy includes one of: Cu ₂ MnAl, Cu ₂ MnIn, Cu ₂ MnSn, Ni ₂ MnAl, Ni ₂ MnIn, Ni ₂ MnSn, Ni ₂ MnSb, Ni ₂ MnGa Co ₂ MnAl, Co ₂ MnSi, Co ₂ MnGa, Co ₂ MnGe, Pd ₂ MnAl, Pd ₂ MnIn, Pd ₂ MnSn, Pd ₂ MnSb, Co ₂ FeSi, Co ₂ FeAl, Fe ₂ VAl, Mn ₂ VGa, Co ₂ FeGe, MnGa, or MnGaRu.

[00147] Example 40 includes all features of example 38, wherein the Heusler alloy includes one or more of Co, Cu, Fe, Ga, Ge, In, Mn, Al, In, Sb, Si, Sn, Ni, Pd, Ru, or V.

[00148] Example 41 is according to any of examples 30 to 38, wherein the first layer comprises a stack of materials, wherein the materials for the stack include one of: Co and Pt; Co and Pd; Co and Ni; MgO, CoFeB, Ta, CoFeB, and MgO; MgO, CoFeB, W, CoFeB, and MgO; MgO, CoFeB, V, CoFeB, and MgO; MgO, CoFeB, Mo, CoFeB, and MgO; or Mn _x Ga _y .

[00149] Example 42 is according to any of examples 30 to 38, wherein the first layer comprises a single layer of one or more materials.

[00150] Example 43 includes features of example 42, wherein the single layer includes: Mn and Ga.

[00151] Example 44 is a method which comprises: forming a magnetic junction having a first layer, the first layer including free magnetic material; and forming a second layer comprising a material including one or more of Cu, Ir, or Mn, the second layer being adjacent to one end of the first layer.

[00152] Example 45 includes features of example 44, wherein the material is to provide a positive spin Hall angle. [00153] Example 46 is according to any of examples 44 to 45, wherein the material of the second layer is to provide field assist in conjunction with spin orbit coupling to the first layer.

[00154] Example 47 is according to any of examples 44 to 45, wherein the material of the second layer includes one of: CuPt, IrMn, Culr, or PtMn.

[00155] Example 48 is according to any of examples 44 to 45, wherein the free magnetic material comprises a material having anisotropy effective field Hk in a range of 50 Oe to 500 Oe.

[00156] Example 49 is according to any of examples 44 to 45 comprises a spin wave generator adjacent to the second layer.

[00157] Example 50 includes all features of example 49, wherein the spin wave generator comprises at least one of: an antenna, a tunneling magnetoresistance (TMR) device, or a magnetoelectric device.

[00158] Example 51 is according to any of examples 44 to 45 comprises a spin wave detector adjacent to another end of the first layer.

[00159] Example 52 includes features of example 44, wherein the first layer comprises one or a combination of materials which include one of: a Heusler alloy, Co, Fe, Ni, Gd, B, Ge, Ga, permalloy, or Yttrium Iron Garnet (YIG).

[00160] Example 53 includes features of example 52, wherein the Heusler alloy is a material which includes one of: Cu ₂ MnAl, Cu ₂ MnIn, Cu ₂ MnSn, Ni ₂ MnAl, Ni ₂ MnIn, Ni ₂ MnSn, Ni ₂ MnSb, Ni ₂ MnGa Co ₂ MnAl, Co ₂ MnSi, Co ₂ MnGa, Co ₂ MnGe, Pd ₂ MnAl, Pd ₂ MnIn, PdJVInSn, PdJVInSb, Co ₂ FeSi, Co ₂ FeAl, Fe ₂ VAl, Mn ₂ VGa, Co ₂ FeGe, MnGa, or MnGaRu.

[00161] Example 54 includes features of example 44, wherein the first layer comprises a stack of materials, and wherein the materials for the stack include one of: Co and Pt; Co and Pd; Co and Ni; MgO, CoFeB, Ta, CoFeB, and MgO; MgO, CoFeB, W, CoFeB, and MgO; MgO, CoFeB, V, CoFeB, and MgO; MgO, CoFeB, Mo, CoFeB, and MgO; or Mn _x Ga _y .

[00162] Example 55 includes features of example 44, wherein the first layer comprises a single layer of one or more materials. Example 56 includes features of example 55, wherein the single layer includes: Mn and Ga. An abstract is provided that will allow the reader to ascertain the nature and gist of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.