Technical Field

Embodiments described herein generally relate to controlling a voltage. More particularly, although not exclusively, embodiments relate to controlling a voltage provided to one or more loads from one or more energy harvesting circuits.

Background

Electrical energy for loads can be provided from a number of sources including energy harvesting sources and energy storage sources. Energy harvesting sources harvest energy from an ambient environment, such as solar or kinetic energy. Energy storage sources include batteries. Each source may have different characteristics, particularly relating to a voltage of supplied electrical energy. For example, electrical energy from harvesting sources may vary from 0.1 to 5 Volts depending upon a type of the harvesting source. Similarly, energy storage sources may have a variety of voltages such as 2.7-4.2 Volts for a Li-ION battery as an example. It will be appreciated that these voltage ranges are provided for illustration and are not restrictive. Similarly, different loads have different supply voltage requirements. These may be from 1.8-3.3 Volts for sensors and input- output devices to 1 Volts and below for computational circuitry.

Brief Description of the Drawings

Embodiments described herein are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements:

Figure 1 schematically illustrates voltage control circuitry according to an embodiment of the invention;

Figure 2 schematically illustrates voltage conversion circuitry according to an embodiment of the invention;

Figure 3 schematically illustrates timing in voltage control circuitry operative as a buck converter;

Figure 4 schematically illustrates timing in voltage control circuitry operative as a boost converter;

Figure 5 schematically illustrates timing in voltage control circuitry operative as a down converter;

Figure 6 schematically illustrates timing in voltage control circuitry operative as an up converter; Figure 7 schematically illustrates timing in time-multiplexed voltage control circuitry; and

Figure 8 schematically illustrates topology arbitration circuitry according to an embodiment of the invention.

Description of Embodiments

Illustrative embodiments of the present disclosure include, but are not limited to, methods, systems, apparatuses and machine readable instructions for controlling power provided to one or more loads.

Figure 1 schematically illustrates voltage control circuitry 100 according to an embodiment of the invention. The voltage control circuitry 100 comprises voltage conversion circuitry 110, efficiency control circuitry 120, topology arbitration circuitry 130 and output control circuitry 140.

As will be explained in more detail with reference to Figure 2, the voltage conversion circuitry 110 comprises one or more inputs 111, 112, 113. In the example shown in Figure 1 the voltage conversion circuitry 110 comprises three inputs 111, 112, 113 although it will be appreciated that this is merely illustrative and that the voltage conversion circuitry 110 may comprise one input or two or more inputs. The voltage conversion circuitry 110 may comprise N inputs 111, 112, 113 where N is an integer.

Each input 111, 112, 113 is arranged to receive power from a respective power source (not shown). At least some of the power sources may be harvesting power sources which harvest, or convert, power from an ambient environment. The harvesting power sources may convert kinetic energy i.e. movement into electrical energy, such as vibration, switch actuation, wind or hydro power, or may convert radiation energy, such as solar, into electrical energy. Other forms of harvesting power sources may be envisaged. A characteristic of such harvesting power sources is a wide variety of voltages of the generated power. For example, such harvesting power sources may provide electrical energy with voltages in the range of 0.5 to 5 Volts, although embodiments of the invention are not limited in this respect. One or more of the power sources may be a power storage device such as a battery. The battery may have provide power within a voltage range, such as 2.7-4.2 Volts for a Li-ION battery. Thus each power source provides power, when operable, at an associated voltage or within an associated voltage range. When the voltage conversion circuitry 110 comprises a plurality of inputs 111, 112, 113 it will be appreciated that at different times, due to the nature of harvesting power sources, different ones of the power sources, or different combinations of power sources, may be provide power to the voltage conversion circuitry 110. The voltage conversion circuitry 110 comprises one or more outputs 115, 116, 117. In the example shown in Figure 1 the voltage conversion circuitry 110 comprises three outputs 115, 116, 117 although it will be appreciated that this is merely illustrative and that the voltage conversion circuitry 110 may comprise one output or two or more outputs. The voltage conversion circuitry may comprise M outputs where M is an integer.

The inputs 115, 116, 117 are arranged to operatively provide power to the one or more loads. The one or more loads may comprise, for example, a sensor. It will be appreciated that the one or more loads may be any electrical component or device which operatively consumes power.

The voltage conversion circuitry 110 is arranged to control one or more characteristics of the power provided to the one or more outputs 115, 116, 117. In some embodiments, the one or more characteristics of the power provided to the one or more outputs 115, 116, 117 comprises a voltage at the one or more outputs 115, 116, 117. The voltage conversion circuitry 110 may control the voltage at the one or more outputs 115, 116, 117 with respect to the voltage at the one or more inputs 111, 112, 113, as will be explained. In some embodiments, the control comprises selectively increasing or up-converting the voltage at the one or more inputs 111, 112, 113 or selectively decreasing or down-converting the voltage at the one or more inputs 111, 112, 113 for provision to the one or more outputs 115, 116, 117.

The voltage control circuitry 100 comprises efficiency control circuitry 120 which is arranged to determine a voltage at each of the one or more inputs 111, 112, 113 from the one or more power sources, and a voltage at each of the one or more outputs 115, 116, 117 provided to the one or more loads. The efficiency control circuitry 120 is arranged to select one of a plurality of predetermined topologies, or configurations, of the voltage conversion circuitry 110. The efficiency control circuitry 120 selects the topology in dependence on the voltages at each of the one or more inputs 111, 112, 113 and the one or more outputs 115, 116, 117. In some embodiments, the efficiency control circuitry 120 may determine one or more of the one or more inputs 111, 112, 113 from which power is to be used. That is, the efficiency control circuitry 120 may select some of the inputs 111, 112, 113 from which to use power, as will be explained.

The voltage control circuitry 100 comprises topology arbitration circuitry 130 which is arranged to configure the voltage conversion circuitry 110 in the selected topology. The topology arbitration circuitry 130 is arranged to receive an indication of the selected topology from the efficiency control circuitry 120. The topology arbitration circuitry 130, in dependence on the indication, configures the voltage conversion circuitry 110, as will be explained.

The voltage control circuitry 110 comprises output control circuitry 140 to control the voltage conversion circuitry 110 in said selected topology to provide the power to the one or more outputs 115, 116, 117 having the one or more characteristics, such as at a voltage appropriate for the one or more loads. That is, within each of the plurality of topologies the output control circuitry 140 is arranged to control the voltage conversion circuitry 110 to provide the one or more outputs 115, 116, 117 with power at a desired voltage or within a desired voltage range.

In some embodiments the voltage control circuitry 100 comprises multiplexing circuitry 150 and analog-to-digital conversion circuitry 160. The multiplexing circuitry 150 and analog- to-digital conversion circuitry 160 is arranged to provide the efficiency control circuitry 120 with an indication of voltages at each of the one or more inputs 111, 112, 113 and the one or more outputs 115, 116, 117 of the voltage conversion circuitry 110.

The multiplexing circuitry 150 is arranged to receive a voltage at each of the one or more inputs 111, 112, 113 and the one or more outputs 115, 116, 117 of the voltage conversion circuitry 110. The multiplexing circuitry 150 operatively multiplexes the received voltages and outputs multiplexed voltages at an output of the multiplexing circuitry 150. The multiplexed voltages comprise a sequential series of voltages corresponding to those at the one or more inputs 111, 112, 113 and the one or more outputs 115, 116, 117 of the voltage conversion circuitry 110.

The analog-to-digital conversion circuitry 160 is arranged to receive the multiplexed voltages from the multiplexing circuitry 150 and to output a digital representation thereof. The digital representation is provided to the efficiency control circuitry 120. In some embodiments, the digital representation may be provided to the output control circuitry 140. As will be appreciated, the analog-to-digital conversion circuitry 160 determines a digital value corresponding to a voltage present at its input. Thus in the arrangement of the voltage control circuitry 100, the analog-to-digital conversion circuitry 160 outputs a series of digital values corresponding to the voltages at the one or more inputs 111, 112, 113 and the one or more outputs 115, 116, 117 of the voltage conversion circuitry 110 provided by the multiplexing circuitry 150.

The efficiency control circuitry 120 may select one of the topologies supported by the voltage conversion circuitry in dependence on the received digital values. In one embodiment, the efficiency control circuitry 120 may store a data storage structure, such as a look-up-table, which is used by the efficiency control circuitry 120 to select one of the topologies in dependence on the received digital values indicative of the voltages at the one or more inputs 111, 112, 113 and the one or more outputs 115, 116, 117 of the voltage conversion circuitry 110. In some embodiments, the efficiency control circuitry 120 selects one or more of the inputs 111, 112, 113 from which power is to be provided to the one or more loads.

Referring to Figure 2, there is shown voltage conversion circuitry 110 according to an embodiment of the invention. Figure 2 represents an expanded view of the voltage conversion circuitry 110 shown in Figure 1.

The voltage conversion circuitry 110 shown in Figures 1 and 2 comprises input circuitry 210 to select one or more of the plurality of inputs 111, 112, 113. The topology arbitration circuitry 130 is arranged to control the input circuitry 210 to select the one or more of the plurality of inputs 111, 112, 113. The selection of the one or more inputs 111, 112, 113 to the voltage conversion circuitry 110 is associated with the configuration of the topology of the voltage conversion circuitry 110. As noted above, the configuration of the voltage conversion circuitry 110 is performed dependent on an input from the efficiency control circuitry 120 provided to the topology arbitration circuitry 130. The input circuitry may comprise a plurality of switching devices 211, 212, 213. As illustrated in Figures 1 and 2, each of the inputs 111, 112, 113 may be associated with a respective switching device 211, 212, 213. The switching devices may be referred to as S,i, S,2, S,3...SiM, where M is the number of inputs as noted above.

The voltage conversion circuitry 110 comprises output circuitry 220 to select one or more of the plurality of outputs 115, 116, 117. The topology arbitration circuitry 130 is arranged to control the output circuitry 220 to select the one or more of the plurality of outputs 115, 116, 117. The selection of the one or more outputs 115, 116, 117 of the voltage conversion circuitry 110 is associated with the configuration of the topology of the voltage conversion circuitry 110. As noted above, the configuration of the voltage conversion circuitry 110 is performed dependent on an input from the efficiency control circuitry 120 provided to the topology arbitration circuitry 130. As illustrated in Figures 1 and 2, each of the outputs 115, 116, 117 may be associated with a respective switching device 221, 222, 223. The switching devices may be referred to as S ₀ i, S ₀ 2, S ₀ 3 - Si , where N is the number of outputs as noted above.

It will be appreciated that selecting one or more of the more of the plurality of inputs 111, 112, 113 and one or more of the plurality of outputs 115, 116, 117 may be understood to mean selectively enabling the one or more of the more of the plurality of inputs 111, 112, 113 and one or more of the plurality of outputs 115, 116, 117. Thus it will be appreciated that the topology arbitration circuitry 130 is operative to selectively enable some or all of the plurality of inputs 111, 112, 113 to the voltage conversion circuitry 110. Those inputs most appropriate to provide the outputs to the one or more loads via the one or more outputs 115, 116, 117 of the voltage conversion circuitry 110 may be enabled by the topology arbitration circuitry 130.

In some embodiments the voltage conversion circuitry 110 comprises reactive circuitry 230. The reactive circuitry 230 comprises a capacitor 231 and an inductor 232. In some embodiments, the reactive circuitry 230 comprises only one capacitor 231 and only one inductor 232 which, advantageously, may serve more than one input 111, 112, 113 and/or outputs 115, 116, 117 of the voltage conversion circuitry 110.

The reactive circuitry 230 is selectively configurable, in some embodiments, as an inductive voltage converter. The inductive voltage converter may be one of a buck or boost circuit. In some embodiments, the reactive circuitry 230 is selectively configurable as a capacitive voltage converter, such as a switch capacitor topology. In some capacitive converter topologies the inductor 232 may be bypassed by operation of one or more switching devices, as will be explained, such as S& in the illustrated embodiment.

The voltage conversion circuitry 110 comprises a plurality of switching devices, generally denoted as 235. The plurality of switching devices 235 are operable by one or both of the topology arbitration circuitry 130 and the output control circuitry 140 to select the topology of the voltage conversion circuitry 110 and to control the one or more characteristics of the power provided to the one or more outputs 115, 116, 117. In particular, in some embodiments, the topology of the voltage conversion circuitry 110 is selected from one of buck and boost, although other topologies may be envisaged as discussed below. In some embodiments, the one or more characteristics comprise a voltage of the power provided to the one or more outputs 115, 116, 117 by the voltage conversion circuitry.

The plurality of switching devices 235 is arranged to control a relative configuration of the capacitor 231, the inductor 232, ground, an input voltage V _in from the one or more inputs 111, 112, 113 and an output voltage V _ou t provided to the one or more outputs 115, 116, 117. In the embodiment shown in Figures 1 and 2, the voltage conversion circuitry 110 comprises seven switching devices Si, S ₂ , S3...S7. However it will be realized that other numbers of switching devices may be envisaged.

The voltage conversion circuitry 110 may be operative in a selected topology in a plurality of phases. Between each phase at least some of the switching devices 235 may be reconfigured such that the output voltage V _ou t is controlled. The output voltage V _ou t may be configured to be down converted from the input voltage V _in or up converted from the input voltage V _in . A relative timing of the plurality of phases provides control over the output voltage V _ou t- In some embodiments, first and second phases of operation of the voltage conversion circuitry 110 may be controlled by the output control circuitry 140. A duty cycle of the first and second phases may be controlled by the output control circuitry 140 to control the output voltage V _ou t- The duty cycle determines a conversion ratio between the input voltage V _in and the output voltage V _ou t-

Figure 3 illustrates timing in the voltage conversion circuitry 110 operative in a buck convertor topology.

The timing comprises first 310 and second 320 illustrated cycles of operation each comprises first Φι and second Φ ₂ phases. The first and second cycles 310, 320 may be separated by one or more further cycles, as indicated. Table 1 below identifies a configuration of switching devices in each of the first Φι and second Φ ₂ phases in the buck conversion topology. A relative duty cycle between the first Φι and second Φ ₂ phases i.e. a relative duration of each phase determines a conversion ratio, as noted above. The upper trace in Figure 3 illustrates those switches that are ON in the first phase Φι, as indicated in the table below. The lower trace in Figure 3 illustrates those switches that are

ON in the second phase Φ ₂ .

Table 1: Switching device configuration in buck conversion topology

In the above, when Si, S ₂ are ON, S3 and S ₄ are off and visa-versa. Switches Si, S ₂ , S3 and S ₄ bypass the capacitor 231 when ON. In some embodiments, including in the configurations discussed below, only one input SU-SI is on at any one time to prevent shorting between inputs. However in some embodiments, a plurality of inputs may be on at different times during the first phase Φι, as discussed further below.

Figure 4 illustrates timing in the voltage conversion circuitry 110 operative in a boost convertor topology. The timing comprises first 410 and second 420 illustrated cycles of operation each comprises first Φι and second Φ ₂ phases. The first and second cycles 410, 420 may be separated by one or more further cycles, as indicated. Table 2 below identifies a configuration of switching devices in each of the first Φι and second Φ ₂ phases in the boost conversion topology. A relative duty cycle between the first Φι and second Φ ₂ phases i.e. a relative duration of each phase determines a conversion ratio.

Table 2: Switching device configuration in boost conversion topology

In the above, in the first phase Φι, when Si, S ₂ and S7 are ON, S3, S ₄ , and S5 are OFF and the second phase Φ ₂ , S ₃ , S ₄ , S5 and S7 are OFF.

In some embodiments, the voltage conversion circuitry 110 may be configured in a switched capacitor topology. The switched capacitor topology may be one of an up- convertor or a down-convertor. In the switched capacitor topology one or more switching devices are arranged to bypass the inductor 232. The switching device Se may be configured to be on i.e. short-circuit to bypass the inductor 232 in all phases in the illustrated embodiment. The switched capacitor topology will be explained with reference to Figures 5 and 6.

Figure 5 illustrates timing in the voltage conversion circuitry 110 operative in a down converter switched capacitor topology. The down converter may be a 2: 1 down converter. The timing comprises first 510 and second 520 illustrated cycles of operation each comprises first Φι and second Φ ₂ phases. The first and second cycles 510, 520 may be separated by one or more further cycles, as indicated. Table 3 below identifies a configuration of switching devices in each of the first Φι and second Φ ₂ phases in the down converter switched capacitor topology.

Table 3: Switching device configuration in a down convertor switched capacitor topology

Figure 6 illustrates timing in the voltage conversion circuitry 110 operative in an up- convertor switched capacitor topology. The up convertor may be a 2: 1 up convertor. The timing comprises first 610 and second 620 illustrated cycles of operation each comprises first Φι and second Φ2 phases. The first and second cycles 610, 620 may be separated by one or more further cycles, as indicated. Table 4 below identifies a configuration of switching devices in each of the first Φι and second Φ2 phases in the up convertor switched capacitor topology.

Table 4: Switching device configuration in an up convertor switched capacitor topology

In addition to the above switched capacitor topologies, the inductor 232 may utilized to form a three-level inductor-based buck convertor. In such a topology, the inductor bypass switch, S6, is controlled to be at least partially off.

To operate as linear regulator, the switches Si, S2 and S& need to be partially turned on to present a variable series resistance i.e. to have some non-zero resistance at all times. This can also be obtained by using a binary-weighted bank of switches that are digitally controlled.

Figure 7 illustrates temporal scheduling of power. Temporal scheduling may allow one or both of power to be provided from a plurality of power sources and provided to a plurality of loads. The upper portion of Figure 7 illustrates input power selection whilst the lower portion of Figure 7 illustrates output power selection. It will be realized that embodiments may be envisaged which include only one, or both, of input and output power selection. Temporal scheduling represents time-multiplexing of one, or both, of power from multiple inputs or provided to multiple outputs. In some embodiments, only one input selected at any point in time. Temporal scheduling of input power may be useful in applications where, for example, a harvesting power source only harvests a low amount of power which is used to, for example, charge a power storage device such as a capacitor. In such cases, the power stored in the storage device may be consumed relatively quickly. Thus switching to another power source may be useful. Similarly, when a load is consuming a relatively small amount of power, power may be sequentially provided to more than one load in the form of energy packets.

Referring to Figure 7, during a first period 701 a first input 111 is connected to a first power source at a first time to provide input power. During a second period 702 a second input 112 is connected to a second power source to provide power. During a third period 703 701 a third input 113 is connected to a third power source at a third time to provide input power. The first, second and third inputs 111, 112, 113 are sequentially selected in a time- multiplexed manner. In a left-hand side of Figure 7 power from the first, second and third power sources is provided to one output, such as output 115, to a first load during a first output period 711.

In a right hand side of Figure 7, one input is selected to provide power to a plurality of outputs in a time-multiplexed manner. One input, such as input 111, is selected during period 703. Meanwhile during three output periods 712, 713, 711 power is provided sequentially to three loads via outputs 115, 116, 117. It will be appreciated that embodiments of the invention are not limited to three inputs and three outputs and other numbers may be envisaged.

Figure 8 illustrates topology arbitration circuitry 800 according to an embodiment of the invention. The topology arbitration circuitry 800 shown in Figure 8 comprises a current detector 810 and a switch driver 820. The current detector 810 is provided with an input 815 indicative of a current in the voltage conversion circuitry 110. In some embodiments, which may be switched inductor embodiments, the current may be a current flowing through the inductor 232. In said embodiments the current detector 810 is arranged to determine when the input 815 is indicative of a predetermined current. In some embodiments the predetermined current is substantially zero. Thus, in these embodiments, switching may occur when substantially no current flows through the inductor 232. The current detector 810 is arranged to provide a signal to the switch driver 820 indicative of the current in the voltage conversion circuitry being the predetermined current, such that the switch driver may cause a change in the topology of the voltage conversion circuitry 110 at an appropriate point in time. The switch driver 820 is provided with an input 825 indicative of a selected topology from the efficiency control circuitry 120. Based on the input 825, the switch driver outputs a signal 830 to control a position of one or more switching devices 211, 212, 213, 221, 222, 223, 235. The switch driver 820 may output a signal indicative of a selection of one of the switching devices 211, 212, 213 selecting one of the inputs 111, 112, 113. The switch driver 820 may output a signal 830 indicative of a selection of one of the switching devices 221, 222, 223 selecting one of the outputs 115, 116, 117. Furthermore, the switch driver 820 may output a signal 830 indicative of switching devices 235 arranged to determine the topology of the voltage conversion circuitry 110. However in other embodiments, which may be switched capacitor embodiments, the input 815 may not be required since it is not necessary to switch at a predetermined current in the voltage conversion circuitry 110.

It can be appreciated that voltage control circuitry according to embodiments of the invention may be used to manage power provided from one or more power sources to one or more loads. Embodiments of the present invention may be useful in net zero systems where a total amount of energy consumed by the one or more loads is generally equal to an amount of energy produced by one or more harvesting energy sources. In contrast to using a predetermined voltage conversion topology, embodiments of the invention may adapt to changes in power consumption of the one or more loads and power generation by the one or more power sources. In particular, embodiments of the invention may handle a large dynamic range of load conditions.

Where functional units have been described as circuitry, the circuitry may be general purpose processor circuitry configured by program code to perform specified processing functions. The circuitry may also be configured by modification to the processing hardware. Configuration of the circuitry to perform a specified function may be entirely in hardware, entirely in software or using a combination of hardware modification and software execution. Program instructions may be used to configure logic gates of general purpose or special-purpose processor circuitry to perform a processing function. Circuitry may be implemented, for example, as a hardware circuit comprising custom Very Large Scale Integrated, VLSI, circuits or gate arrays, off-the-shelf semiconductors such as logic chips, transistors, or other discrete components. Circuitry may also be implemented in programmable hardware devices such as field programmable gate arrays, FPGA, programmable array logic, programmable logic devices, A System on Chip, SoC, or the like. Machine readable program instructions may be provided on a transitory medium such as a transmission medium or on a non-transitory medium such as a storage medium. Such machine readable instructions (computer program code) may be implemented in a high level procedural or object oriented programming language. However, the program(s) may be implemented in assembly or machine language, if desired. In any case, the language may be a compiled or interpreted language, and combined with hardware implementations.

Examples

The following examples pertain to the present technique.

Example 1 is voltage control circuitry to control a voltage provided to one or more loads, the voltage control circuitry comprising:

voltage conversion circuitry having one or more inputs to receive power from each of one or more power sources, and one or more outputs to provide power to each of the one or more loads, wherein the voltage conversion circuitry is arranged to control one or more characteristics of the power provided to the one or more outputs;

efficiency control circuitry to determine a voltage at each input from the one or more power sources and a voltage at each output provided to the one or more loads and to select one of a plurality of predetermined topologies of the voltage conversion circuitry in dependence thereon;

topology arbitration circuitry to receive an indication of the selected topology and to configure the voltage conversion circuitry in said topology; and

voltage control circuitry to control the voltage conversion circuitry in said topology to provide the power to the one or more outputs having the one or more characteristics. Example 2 may be the subject matter of example 1, wherein the voltage control circuitry comprises a plurality of inputs to each receive a power input from one of a plurality of power sources, the voltage control circuitry comprising:

input circuitry to select one of the plurality of inputs;

wherein the topology arbitration circuitry is arranged to control the input circuitry to select the one of the plurality of inputs in dependence on an input from the efficiency control circuitry. Example 3 may be the subject matter of example 1 or 2, wherein the voltage control circuitry comprises a plurality of outputs to each output provide power to one of a plurality of loads, the voltage control circuitry comprising:

output circuitry to select one or more of the plurality of outputs;

wherein the topology arbitration circuitry is arranged to control the output circuitry to select the one or more of the plurality of outputs in dependence on an input from the efficiency control circuitry.

Example 4 may be the subject matter of any of examples 1 to 3, comprising:

multiplexing circuitry to multiplex a voltage at the one or more inputs and the one or more outputs of the voltage conversion circuitry and to output multiplexed voltages; analog-to-digital conversion circuitry to receive the multiplexed voltages and to generate digital representations of the multiplexed voltages;

wherein the efficiency computation circuitry is arranged receive the digital representations of the multiplexed voltages and to determine the topology of the voltage conversion circuitry in dependence thereon.

Example 5 may be the subject matter of example 4, wherein the efficiency computation circuitry is to select the topology of the voltage conversion circuitry in dependence on the voltage at each of the one or more inputs to the voltage conversion circuitry and each of the outputs of the voltage conversion circuitry.

Example 6 may be the subject matter of any of examples 1 to 5, wherein the plurality of predetermined topologies of the voltage conversion circuitry comprise buck and boost topologies to control a voltage of the power provided from the one or more power sources to the one or more inputs.

Example 7 may be the subject matter of any of examples 1 to 6, wherein the one or more characteristics of the power provided to the one or more outputs comprise a voltage of the one or more outputs.

Example 8 may be the subject matter of any of examples 1 to 7, wherein the voltage conversion circuitry comprises a capacitor, an inductor and a plurality of switching devices operable by the control circuitry to provide the power to the one or more outputs.

Example 9 may be the subject matter of example 8, wherein one or more of the plurality of switching devices are arranged to selectively connect the capacitor to the one or more inputs.

Example 10 may be the subject matter of example 8 or 9, wherein one or more of the plurality of switching devices are arranged to bypass the inductor to selectively connect the capacitor to the one or more outputs. Example 11 may be the subject matter of any of examples 1 to 10, wherein the topology arbitration circuitry is arranged to receive an indication of one or more measurements of the power in the voltage conversion circuitry and to change the configuration of the voltage conversion circuitry in dependence thereon.

Example 12 is a power supply for one or more electronic loads, comprising:

first second power sources;

voltage conversion circuitry having a first input electrically connected to the first power source and a second input electrically connected to the second power source to receive power from each of the first and second power sources, respectively, input circuitry to select one of the first and second inputs, and one or more outputs to provide power to each of the one or more loads, wherein the voltage conversion circuitry is arranged to control one or more characteristics of the power provided to the one or more outputs; efficiency control circuitry to determine a voltage at each of the first and second inputs from the first and second power sources, and a voltage at each output provided to the one or more loads and to select one of a plurality of predetermined topologies of the voltage conversion circuitry in dependence thereon;

topology arbitration circuitry to receive an indication of the selected topology and to configure the voltage conversion circuitry in said topology and to select one of the first and second inputs; and

voltage control circuitry to control the voltage conversion circuitry in said topology to provide the power to the one or more outputs having the one or more characteristics. Example 13 may be the subject matter of example 12, comprising first and second outputs electrically connected to first and second loads, respectively, wherein the voltage control circuitry comprises output circuitry to select one of the first and second outputs, wherein the topology arbitration circuitry is arranged to control the voltage control circuitry to sequentially select the first input and the second input to provide power to one of the first and second outputs.

Example 14 may be the subject matter of example 12 or 13, wherein the topology arbitration circuitry is arranged to control the configuration of the voltage conversion circuitry in said selected topology.

Example 15 may be the subject matter of any of examples 12 to 14, wherein the topology arbitration circuitry is arranged to receive an indication of one or more currents in the voltage conversion circuitry and to change the configuration of the voltage conversion circuitry in dependence thereon.

Example 16 may be the subject matter of any of examples 12 to 15, comprising: multiplexing circuitry to multiplex a voltage at each of the first and second inputs and the one or more outputs of the voltage conversion circuitry and to output multiplexed voltages;

analog-to-digital conversion circuitry to receive the multiplexed voltages and to generate digital representations of the multiplexed voltages;

wherein the efficiency computation circuitry is arranged receive the digital representations of the multiplexed voltages and to determine the topology of the voltage conversion circuitry in dependence thereon.

Example 17 may be the subject matter of any of examples 12 to 16, wherein the plurality of predetermined topologies of the voltage conversion circuitry comprise buck and boost topologies to respectively reduce and increase a voltage of the power provided from the one or more power sources to the one or more inputs.

Example 18 may be the subject matter of any of examples 12 to 17, wherein the one or more characteristics of the power provided to the one or more outputs comprise a voltage of the one or more outputs.

Example 19 may be the subject matter of any of examples 12 to 18, wherein the voltage conversion circuitry comprises at least one capacitor, at least one inductor and a plurality of switching devices operable by the control circuitry to provide the power to the one or more outputs at the voltage.

Example 20 may be the subject matter of example 19, wherein the voltage conversion circuitry comprises only one capacitor and only one inductor, wherein one or more of the plurality of switching devices are arranged to connect the capacitor to the one or more inputs.

Example 21 may be the subject matter of example 20, wherein one or more of the plurality of switching devices are arranged to bypass the inductor to connect the capacitor to the one or more outputs.

Example 22 is machine-readable instructions provided on at least one machine-readable medium, the machine readable instructions, when executed, to cause processing hardware to:

determine a voltage at each of one or more inputs from one or more power sources and a voltage at each of one or more outputs provided to one or more electrical loads; select one of a plurality of predetermined topologies of voltage conversion circuitry to control one or more characteristics of the power provided to the one or more outputs; configure the voltage conversion circuitry in said selected topology; control the voltage conversion circuitry in said selected topology to provide power to the one or more outputs having one or more desired characteristics.

Example 23 may be the subject matter of example 22 comprising instructions to cause the processing hardware to select a first one of the or more inputs in dependence on the voltage at each of the one or more inputs.

Example 24 may be the subject matter of example 22 or 23, comprising instructions to cause the processing hardware to determine one or more characteristics of the power in the voltage conversion circuitry and to reconfigure the voltage conversion circuitry in dependence thereon.

Example 25 may be the subject matter of example 24, wherein the reconfiguration of the voltage conversion circuitry comprises selecting a second one of the one or more inputs.