SEMICONDUCTOR CHIP WITH IDENTIFICATION CODES, MANUFACTURING METHOD OF THE CHIP AND SEMICONDUCTOR CHIP MANAGEMENT SYSTEM

Title:

SEMICONDUCTOR CHIP WITH IDENTIFICATION CODES, MANUFACTURING METHOD OF THE CHIP AND SEMICONDUCTOR CHIP MANAGEMENT SYSTEM

Document Type and Number:

WIPO Patent Application WO2006064921

Kind Code:

A3

Abstract:

There is provided a semiconductor chip using an electrical identification code and an optical identification code, both of the codes being formed in the same process to be always in one-to-one correspondence with each other. An optically readable wiring pattern associated with an electrically readable identification code is formed on a top layer of the semiconductor chip or a layer that is optically identifiable from the top layer, and used as an optical identification code. The semiconductor chip is thus provided such that the optically readable wiring pattern is part of wiring of memory elements that electrically store an identification code, and comprised of a combination of wiring forms set as 1 or 0 that is an output of each of the memory elements.

Inventors:

HAYASHI HIROAKI (JP)
INANAMI RYOICHI (JP)
KISHIMOTO KATSUMI (JP)

Application Number:

PCT/JP2005/023185

Publication Date:

October 26, 2006

Filing Date:

December 12, 2005

Export Citation:

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Assignee:

BEAM CORP E (JP)
HAYASHI HIROAKI (JP)
INANAMI RYOICHI (JP)
KISHIMOTO KATSUMI (JP)

International Classes:

H01L23/544

Foreign References:

US5301143A	1994-04-05
US20030181025A1	2003-09-25

Other References: