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Patent Searching and Data


Title:
SEMICONDUCTOR DEVICE AND BONDING METHOD
Document Type and Number:
WIPO Patent Application WO/2024/047959
Kind Code:
A1
Abstract:
The purpose of the present invention is to provide a semiconductor device having low electrical resistance while preventing defects in semiconductor elements caused by thermal expansion differences by laminating an Fe-Ni alloy metal layer directly or indirectly on the front electrode or back electrode of a semiconductor element. An Fe-Ni alloy metal layer 5 is deposited directly or indirectly on the front electrode and/or the back electrode of the semiconductor chip 2, and the semiconductor chip and a conductor 4 are connected through the Fe-Ni alloy metal layer 5. If necessary, the amount of Ni in the Fe-Ni alloy metal layer 5 is in the range of 36-45 wt%, and the thickness of the Fe-Ni alloy metal layer 5 is 2-20 μm.

Inventors:
TATSUMI KOHEI (JP)
KOSHIBA KEIKO (JP)
Application Number:
PCT/JP2023/018085
Publication Date:
March 07, 2024
Filing Date:
May 15, 2023
Export Citation:
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Assignee:
UNIV WASEDA (JP)
International Classes:
H01L21/52; H01L21/60; H01L23/12; H01L23/48
Foreign References:
JP2006179735A2006-07-06
JP2010225852A2010-10-07
US20120248176A12012-10-04
JP2002305213A2002-10-18
JPH02275657A1990-11-09
JPS61268032A1986-11-27
JP2017005037A2017-01-05
JP2011198796A2011-10-06
Attorney, Agent or Firm:
HIRAI Yasuo (JP)
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