Title:
SEMICONDUCTOR DEVICE INSPECTION METHOD AND SEMICONDUCTOR DEVICE INSPECTION DEVICE
Document Type and Number:
WIPO Patent Application WO/2021/241008
Kind Code:
A1
Abstract:
A semiconductor inspection device 1 comprises: a measuring instrument 7 that supplies power to a semiconductor device S and simultaneously measures the electrical characteristics of the semiconductor device S according to the supply of power; an optical scanning device 13 that scans the semiconductor device S with light for which the intensity has been modulated at a plurality of frequencies; a lock-in amplifier 15 that acquires characteristic signals indicating the electrical characteristics at a plurality of frequency components according to the scanning with light; and an inspection device 19 that processes the characteristic signals. The inspection device 19 corrects a phase component of a characteristic signal at any scanning position on the basis of a phase component of a characteristic signal at a scanning position at which is reflected an electrical characteristic of a first layer L1 in the semiconductor device S, identifies a phase component of a characteristic signal at a scanning position at which is reflected an electrical characteristic of a second layer L2 in the semiconductor device S, standardizes the phase component of the characteristic signal at any scanning position by using the identified phase component, and outputs a result based on the standardized phase component of the characteristic signal.
Inventors:
CHINONE NORIMICHI (JP)
NAKAMURA TOMONORI (JP)
SHIMASE AKIRA (JP)
NAKAMURA TOMONORI (JP)
SHIMASE AKIRA (JP)
Application Number:
PCT/JP2021/014505
Publication Date:
December 02, 2021
Filing Date:
April 05, 2021
Export Citation:
Assignee:
HAMAMATSU PHOTONICS KK (JP)
International Classes:
G01R31/319
Domestic Patent References:
| WO2018061378A1 | 2018-04-05 | |||
| WO2013008850A1 | 2013-01-17 |
Foreign References:
| JP2016014553A | 2016-01-28 | |||
| JP2011047825A | 2011-03-10 | |||
| JP2016534344A | 2016-11-04 | |||
| JP2013526723A | 2013-06-24 |
Other References:
SCHMIDT, CHRISTIAN ET AL.: "Non-destructive defect depth determination at fully packaged and stacked die devices using Lock-in Thermography", 17TH IEEE INTERNATIONAL SYMPOSIUM ON THE PHYSICAL AND FAILURE ANALYSIS OF INTEGRATED CIRCUITS, 5 July 2010 (2010-07-05), XP031720074, DOI: 10.1109/IPFA.2010.5532004
K. J. P. JACOBS ET AL.: "Lock-in thermal laser stimulation for non-destructive failure localization in 3-D devices", MICROELECTRONICS RELIABILITY, vol. 76, no. 77, 2017, pages 188 - 193
See also references of EP 4148437A4
K. J. P. JACOBS ET AL.: "Lock-in thermal laser stimulation for non-destructive failure localization in 3-D devices", MICROELECTRONICS RELIABILITY, vol. 76, no. 77, 2017, pages 188 - 193
See also references of EP 4148437A4
Attorney, Agent or Firm:
HASEGAWA Yoshiki et al. (JP)
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