SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR

WIPO Patent Application WO/2010/140244

A1

First protective films (16a, 16b) are formed to cover the side surfaces of gate electrode sections (11a, 11b). In an nMOS region (R1), the portion of the first protective film (16a) positioned on the side surface of the gate electrode section (11a) serves as an offset spacer (21a), and cleaning is performed after an extension injection region (23a) is formed using the spacer as a mask. The resistance to chemical solutions is improved by forming silicon nitride films (15a, 15b) on the surfaces of the first protective films (16a, 16b). In addition, second protective films (20a, 20b) are formed on the first protective films (16a, 16b), respectively. In a pMOS region (R2), the portion of the second protective film (20b) and the portion of the first protective film (16b) positioned on the side face of the gate electrode section (11b) serve as an offset spacer (21b), and cleaning is performed after an extension injection region (23b) is formed using the spacer as a mask. The resistance to chemical solutions is improved by silicon nitride films (19a, 19b) being formed on the surfaces of the second protective films (20a, 20b).

JPH04159773	INPUT PROTECTIVE CIRCUIT
JPS5923557	METHOD OF PRODUCING COMPLEMENTARY METAL-OXIDE FILM-SEMICONDUCTOR (C-MOS) TRANSISTOR
JP5000055	Semiconductor device

KATO HISAYUKI (JP)
KUSAKABE YOSHIHIKO (JP)

PCT/JP2009/060315

December 09, 2010

June 05, 2009

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RENESAS ELECTRONICS CORP (JP)
KATO HISAYUKI (JP)
KUSAKABE YOSHIHIKO (JP)

H01L21/8238; H01L27/092

JP2001110913A	2001-04-20
JP2006294877A	2006-10-26
JP2008300505A	2008-12-11
JP2004349372A	2004-12-09
JP2008117848A	2008-05-22
JP2005513774A	2005-05-12

FUKAMI, Hisao et al. (JP)
Hisao Fukami (JP)

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