Title:
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR
Document Type and Number:
WIPO Patent Application WO/2015/040938
Kind Code:
A1
Abstract:
This super-junction MOSFET has: a parallel p-n layer (4), said parallel p-n layer (4) having a plurality of p-n junctions (6), in which n-type drift regions (4a) and p-type dividing regions (4b) sandwiched between said p-n junctions (6) are arranged so as to contact each other in an alternating matter; and a MOS gate structure on the top-surface side of said parallel p-n layer (4). An n-type buffer layer contacts the opposite-principal-surface side and has a low impurity concentration, comparable to or less than that of the n-type drift regions (4a). At least one of the p-type dividing regions (4b) in the parallel p-n layer (4) is replaced by an n--type region (4c) that has a lower impurity concentration than the n-type drift regions (4a). This makes it possible to provide a super-junction MOSFET, and a manufacturing method therefor, that has a gentler hard-recovery waveform during reverse recovery. This also makes it possible to provide a super-junction MOSFET, and a manufacturing method therefor, that exhibits a reduced reverse-recovery current (Irp), reduced reverse-recovery time (trr), high-speed switching, and low reverse-recovery losses.
Inventors:
TAMURA TAKAHIRO (JP)
ONISHI YASUHIKO (JP)
ONISHI YASUHIKO (JP)
Application Number:
PCT/JP2014/068632
Publication Date:
March 26, 2015
Filing Date:
July 11, 2014
Export Citation:
Assignee:
FUJI ELECTRIC CO LTD (JP)
International Classes:
H01L29/78; H01L21/322; H01L21/329; H01L21/336; H01L29/06; H01L29/861; H01L29/868
Foreign References:
| JP2008182054A | 2008-08-07 | |||
| JP2012160753A | 2012-08-23 | |||
| JP2003101022A | 2003-04-04 | |||
| JP2008258313A | 2008-10-23 | |||
| JP2004022716A | 2004-01-22 |
Attorney, Agent or Firm:
SAKAI, AKINORI (JP)
Akinori Sakai (JP)
Akinori Sakai (JP)
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