Title:
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
Document Type and Number:
WIPO Patent Application WO/2024/034411
Kind Code:
A1
Abstract:
The present disclosure relates to: a semiconductor device which makes it possible to achieve both the suppression of a short channel effect and an increase in driving capability; and a method for manufacturing same. The semiconductor device comprises a field effect transistor including: a source area and drain area formed on a semiconductor substrate; and a gate electrode having a planar electrode unit which is formed on an upper surface above the semiconductor substrate and two embedded electrode units which are embedded in the semiconductor substrate. The shape of a channel unit between the two embedded electrode units of the field effect transistor is asymmetrically formed in the directions of the source area and the drain area. The present disclosure can be applied to, for example, an amplification transistor for each pixel of a solid-state imaging device.
Inventors:
KIMIZUKA NAOHIKO (JP)
Application Number:
PCT/JP2023/027502
Publication Date:
February 15, 2024
Filing Date:
July 27, 2023
Export Citation:
Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
H01L27/146; H01L21/336; H01L29/78
Domestic Patent References:
| WO2021065587A1 | 2021-04-08 |
Foreign References:
| JP2008192819A | 2008-08-21 | |||
| JPS57172770A | 1982-10-23 | |||
| US20080048267A1 | 2008-02-28 | |||
| US20160172397A1 | 2016-06-16 |
Attorney, Agent or Firm:
NISHIKAWA Takashi et al. (JP)
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