SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

WIPO Patent Application WO/2012/157772

A1

An n-FS layer (14) has, in addition to the total impurity amount of an n--drift layer (1), a total impurity amount, the level of which is such that a depletion layer extended by the application of a rated voltage stops inside the n-FS layer (14). The n-FS layer (14) also has a concentration gradient in which the impurity concentration of the n-FS layer (14) decreases from a p+- collector layer (15) toward a p-base layer (5) and has a diffusion depth of 20 μm or more. Further, an n+-buffer layer (13) is provided between the n-FS layer (14) and the p+- collector layer (15). The peak impurity concentration of the n+-buffer layer (13) is 6 × 1015 cm-3 or more, which is higher than that of the n-FS layer (14), and is one-tenth or less the peak impurity concentration of the p+-collector layer (15). This improves an element breakdown resistance amount and, at the same time, suppresses a thermal runaway breakdown when a short-circuit occurs, and further makes it possible to provide a field-stop (FS) insulated gate bipolar transistor in which turn-on voltage variations are reduced.

YOSHIMURA TAKASHI (JP)
KURIBAYASHI HIDENAO (JP)
ONOZAWA YUICHI (JP)
NAKANO HAYATO (JP)
OZAKI DAISUKE (JP)

PCT/JP2012/062875

November 22, 2012

May 18, 2012

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FUJI ELECTRIC CO LTD (JP)
YOSHIMURA TAKASHI (JP)
KURIBAYASHI HIDENAO (JP)
ONOZAWA YUICHI (JP)
NAKANO HAYATO (JP)
OZAKI DAISUKE (JP)

H01L29/739; H01L21/336; H01L29/78

WO2011052787A1

2011-05-05

JP2004079878A	2004-03-11
JP2002299346A	2002-10-11
JP2002261282A	2002-09-13
JP2002520885A	2002-07-09
JP2010056134A	2010-03-11

See also references of EP 2711986A4

SAKAI, AKINORI (JP)
Akinori Sakai (JP)

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