Title:
SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME
Document Type and Number:
WIPO Patent Application WO/2020/137243
Kind Code:
A1
Abstract:
This semiconductor device is provided with: a gate electrode (5) which is formed on a semiconductor substrate (1), with a gate insulating film (4) being interposed therebetween; an offset drain layer (2) which is provided in the semiconductor substrate (1) on one side of the gate electrode (5); a drain layer (7) which is positioned above the offset drain layer (2); and a source layer (8) which is provided in the semiconductor substrate (1) on the other side of the gate electrode (5). This semiconductor device is also provided with: a protective film (9) which covers the upper surface of the semiconductor substrate (1); a field plate (13) which is provided on the protective film (9) and has a portion that is positioned above the offset drain layer (2); and a field plug (12) which is provided within the protective film (9) so as to be positioned above the offset drain layer (2) without reaching the offset drain layer (2), while being connected to the field plate (13).
Inventors:
SHINDO MASAO (JP)
YAMADA TAKAYUKI (JP)
MOCHO YOSHINOBU (JP)
ICHIKAWA TOSHIHIKO (JP)
INUISHI NORIYUKI (JP)
ICHIMURA HIDEO (JP)
KOIKE NORIO (JP)
LEVIN SHARON (IL)
YANG HONGNING (IL)
MISTELE DAVID (IL)
SHERMAN DANIEL (IL)
YAMADA TAKAYUKI (JP)
MOCHO YOSHINOBU (JP)
ICHIKAWA TOSHIHIKO (JP)
INUISHI NORIYUKI (JP)
ICHIMURA HIDEO (JP)
KOIKE NORIO (JP)
LEVIN SHARON (IL)
YANG HONGNING (IL)
MISTELE DAVID (IL)
SHERMAN DANIEL (IL)
Application Number:
PCT/JP2019/044936
Publication Date:
July 02, 2020
Filing Date:
November 15, 2019
Export Citation:
Assignee:
TOWERJAZZ PANASONIC SEMICONDUCTOR CO LTD (JP)
TOWER SEMICONDUCTOR LTD (IL)
TOWER SEMICONDUCTOR LTD (IL)
International Classes:
H01L29/78; H01L21/336
Foreign References:
| JP2003031804A | 2003-01-31 | |||
| JP2005093775A | 2005-04-07 | |||
| US20160149007A1 | 2016-05-26 |
Attorney, Agent or Firm:
MAEDA & PARTNERS (JP)
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