Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2011/013306
Kind Code:
A1
Abstract:
Disclosed is a semiconductor device which is provided with: a substrate (101); a first nitride semiconductor layer (104S), which is composed of a plurality of nitride semiconductor layers stacked on the substrate (101), and includes a channel region; a second semiconductor layer (105), which is formed on the first nitride semiconductor layer (104S), and has a conductivity type opposite to that of the channel region; a conductive layer, which is formed in contact with the second semiconductor layer (105), and is composed of a metal layer (107) or a high carrier concentration semiconductor layer having a carrier concentration of 1×1018cm-3 or higher; an insulator layer (110) formed on the conductive layer; a gate electrode (111) formed on the insulator layer (110); and a source electrode (108) and a drain electrode (109) which are formed on both the sides of the second semiconductor layer (105).
Inventors:
UMEDA HIDEKAZU
UEDA TETSUZO
UEDA TETSUZO
Application Number:
PCT/JP2010/004515
Publication Date:
February 03, 2011
Filing Date:
July 12, 2010
Export Citation:
Assignee:
PANASONIC CORP (JP)
UMEDA HIDEKAZU
UEDA TETSUZO
UMEDA HIDEKAZU
UEDA TETSUZO
International Classes:
H01L21/337; H01L21/28; H01L21/338; H01L29/06; H01L29/41; H01L29/778; H01L29/78; H01L29/786; H01L29/808; H01L29/812
Foreign References:
| JP2008053312A | 2008-03-06 | |||
| JP2001217257A | 2001-08-10 | |||
| JP2008305894A | 2008-12-18 | |||
| JP2010067816A | 2010-03-25 | |||
| JP2008211172A | 2008-09-11 | |||
| JP2007220895A | 2007-08-30 | |||
| JP2005244072A | 2005-09-08 |
Attorney, Agent or Firm:
MAEDA, Hiroshi et al. (JP)
Hiroshi Maeda (JP)
Hiroshi Maeda (JP)
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