Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2011/021342
Kind Code:
A1
Abstract:
Disclosed is a semiconductor device having a multilayer wiring structure, wherein a dummy pattern is easily manufactured in a wiring space with excellent efficiency. In the relatively small wiring space (Area_S1) in the semiconductor device having the multilayer wiring structure, the dummy pattern (21) is formed in the direction different from that of dummy patterns (22, 23) formed in a relatively large wiring space (Area_S2).
Inventors:
SHIMADA JUNICHI
SHIBATA HIDENORI
FUJII TSUTOMU
FUKAZAWA HIROMASA
IWAUCHI NOBUYUKI
FUJINO TAKEYA
SHIBATA HIDENORI
FUJII TSUTOMU
FUKAZAWA HIROMASA
IWAUCHI NOBUYUKI
FUJINO TAKEYA
Application Number:
PCT/JP2010/004270
Publication Date:
February 24, 2011
Filing Date:
June 28, 2010
Export Citation:
Assignee:
PANASONIC CORP (JP)
SHIMADA JUNICHI
SHIBATA HIDENORI
FUJII TSUTOMU
FUKAZAWA HIROMASA
IWAUCHI NOBUYUKI
FUJINO TAKEYA
SHIMADA JUNICHI
SHIBATA HIDENORI
FUJII TSUTOMU
FUKAZAWA HIROMASA
IWAUCHI NOBUYUKI
FUJINO TAKEYA
International Classes:
H01L21/822; H01L21/3205; H01L21/82; H01L23/52; H01L27/04
Foreign References:
| JP2009146966A | 2009-07-02 | |||
| JP2002368088A | 2002-12-20 | |||
| JP2002110809A | 2002-04-12 | |||
| JP2004022631A | 2004-01-22 | |||
| JP2001237323A | 2001-08-31 | |||
| JP2008282017A | 2008-11-20 | |||
| JP2009182056A | 2009-08-13 |
Attorney, Agent or Firm:
MAEDA, Hiroshi et al. (JP)
Hiroshi Maeda (JP)
Hiroshi Maeda (JP)
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