Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2015/037095
Kind Code:
A1
Abstract:
An IGBT part (10) on which an IGBT is arranged and a circuit part (20) in which a control circuit is arranged are arranged on the same semiconductor chip. A dielectric separation region (40) is arranged on the circuit part (20) at the boundary with the IGBT part (10). A p+-type region (4) is provided on an obverse-surface-side surface layer of the semiconductor chip from the IGBT part (10) to the circuit part (20). A dielectric separation layer (5) is provided to the circuit part (20) at the boundary with the IGBT part (10) from the chip obverse surface through the p+-type region (4) to a depth reaching an n--type drift region (3), the dielectric separation layer (5) constituting the dielectric separation region (40). The p+-type region (4) is divided by the dielectric separation layer (5) into a first p+-type region (4-1) on the IGBT part (10)-side and a second p+-type region (4-2) on the circuit part (20)-side. The first and second p+-type regions (4-1, 4-2) are at a ground potential. It is thereby possible to reduce the size and the cost of the circuit as a whole.
Inventors:
ISHII KENICHI (JP)
NAKAMURA HIROSHI (JP)
NAKAMURA HIROSHI (JP)
Application Number:
PCT/JP2013/074593
Publication Date:
March 19, 2015
Filing Date:
September 11, 2013
Export Citation:
Assignee:
FUJI ELECTRIC CO LTD (JP)
International Classes:
H01L21/8234; H01L21/76; H01L27/088; H01L29/739; H01L29/78
Domestic Patent References:
| WO2010137158A1 | 2010-12-02 | |||
| WO2011024358A1 | 2011-03-03 |
Foreign References:
| JP2011119542A | 2011-06-16 | |||
| JP2006005248A | 2006-01-05 | |||
| JP2012023165A | 2012-02-02 | |||
| JPH05267439A | 1993-10-15 | |||
| JPH11201013A | 1999-07-27 |
Attorney, Agent or Firm:
SAKAI, AKINORI (JP)
Akinori Sakai (JP)
Akinori Sakai (JP)
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