Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2015/162683
Kind Code:
A1
Abstract:
This invention uses surrounding gate transistors (SGTs), which are vertical transistors, to provide a semiconductor device that constitutes a memory-selection decoder and has a small surface area. In said decoder, which comprises an inverter and a two-input NOR decoder comprising six MOS transistors laid out in a single row, each of said MOS transistors is formed on top of a flat silicon layer formed on top of a substrate, wherein a drain, a gate, and a source are arranged vertically, the gate is structured so as to surround a silicon pillar, the flat silicon layer comprises a first activated region that has a first conductivity type and a second activated region that has a second conductivity type, and said regions are connected to each other via a silicon layer formed at the surface of the flat silicon layer, thereby providing a semiconductor device constituting a decoder that has a small surface area.
Inventors:
MASUOKA FUJIO (JP)
ASANO MASAMICHI (JP)
ASANO MASAMICHI (JP)
Application Number:
PCT/JP2014/061241
Publication Date:
October 29, 2015
Filing Date:
April 22, 2014
Export Citation:
Assignee:
UNISANTIS ELECT SINGAPORE PTE (SG)
MASUOKA FUJIO (JP)
ASANO MASAMICHI (JP)
MASUOKA FUJIO (JP)
ASANO MASAMICHI (JP)
International Classes:
H01L21/8242; H01L27/108; H01L29/78; H03K19/0948; H03M7/00
Domestic Patent References:
| WO2011043402A1 | 2011-04-14 | |||
| WO2009096468A1 | 2009-08-06 |
Foreign References:
| JPH03285352A | 1991-12-16 | |||
| JP2008300558A | 2008-12-11 | |||
| JP2007179652A | 2007-07-12 |
Attorney, Agent or Firm:
TSUJII Koichi et al. (JP)
辻居 Koichi (JP)
辻居 Koichi (JP)
Download PDF: