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Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2019/239984
Kind Code:
A1
Abstract:
This semiconductor device comprises: first through N-th PLL circuits which operate in synchronization with a common reference clock signal and which respectively output first through N-th clock signals; a majority circuit that carries out majority calculation with respect to the first through N-th clock signals to generate a majority clock signal; and a filter circuit into which the majority clock signal is input, which operates as a low-pass filter, and which outputs an output clock signal. N is an odd number of 3 or above.

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Inventors:
NARITA TAKANORI (JP)
MATSUURA DAISUKE (JP)
ISHII SHIGERU (JP)
KOBAYASHI DAISUKE (JP)
HIROSE KAZUYUKI (JP)
KAWASAKI OSAMU (JP)
Application Number:
PCT/JP2019/022356
Publication Date:
December 19, 2019
Filing Date:
June 05, 2019
Export Citation:
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Assignee:
MITSUBISHI HEAVY IND LTD (JP)
International Classes:
H03K19/003; G06F1/04; H03K5/00; H03K5/131
Foreign References:
JPH07193495A1995-07-28
JPH06303135A1994-10-28
JPS5934013B21984-08-20
US6728327B12004-04-27
JP2003163583A2003-06-06
JP2018114846A2018-07-26
Other References:
See also references of EP 3748855A4
Attorney, Agent or Firm:
KARINO Yoshimasa (JP)
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