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Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2021/240944
Kind Code:
A1
Abstract:
Provided is a semiconductor device having a semiconductor chip, a semiconductor pattern, a solder alloy layer, and an intermetallic compound layer. The semiconductor pattern consists of a metal (for example, Cu) and is connected to the bottom surface of the semiconductor chip via the solder alloy layer. The intermetallic compound layer is formed at an interface between the bottom surface of the semiconductor chip and the solder alloy layer and includes an uneven surface facing the semiconductor pattern side from the bottom surface side. The bottom surface of the semiconductor chip includes a first region that includes the center of the bottom surface and a second region that includes the outer periphery of the bottom surface. As shown in fig. 2, the thickness of the intermetallic compound layer is such that the average thickness of a portion overlapping with the first region of the bottom surface is greater than the average thickness of a portion overlapping with the second region.

Inventors:
MIYAZAKI TAKAAKI (JP)
YAMASAKI MASANAO (JP)
KUSHIMA TAKAYUKI (JP)
Application Number:
PCT/JP2021/009064
Publication Date:
December 02, 2021
Filing Date:
March 08, 2021
Export Citation:
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Assignee:
HITACHI POWER SEMICONDUCTOR DEVICE LTD (JP)
International Classes:
H01L21/52
Foreign References:
JP2007067158A2007-03-15
JP2011159994A2011-08-18
Attorney, Agent or Firm:
TSUTSUI & ASSOCIATES (JP)
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