Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
WIPO Patent Application WO/2021/182247
Kind Code:
A1
Abstract:
Provided is a layout structure of a capacitive element that uses a forksheet FET. A capacitive structure constituting the capacitive element comprises: a transistor (N11) having a nanosheet (21a) that extends in the X direction, and gate wiring (31a) that extends in the Y direction and surrounds the outer perimeter of the nanosheet (21a); and a transistor (N12) having a nanosheet (21c) that extends in the X direction, and gate wiring (32a) that extends in the Y direction and surrounds the outer perimeter of the nanosheet (21c). The surface on the nanosheet (21c) side of the nanosheet (21a) is exposed from the gate wiring (31a), and the surface on the nanosheet (21a) side of the nanosheet (21c) is exposed from the gate wiring (32a).
Inventors:
SOBUE ISAYA (JP)
Application Number:
PCT/JP2021/008218
Publication Date:
September 16, 2021
Filing Date:
March 03, 2021
Export Citation:
Assignee:
SOCIONEXT INC (JP)
International Classes:
H01L27/04; H01L21/8234; H01L27/06; H01L29/41; H01L29/423; H01L29/49
Domestic Patent References:
| WO2018042986A1 | 2018-03-08 | |||
| WO2018003634A1 | 2018-01-04 | |||
| WO2018025580A1 | 2018-02-08 | |||
| WO2019138546A1 | 2019-07-18 |
Foreign References:
| US20160111337A1 | 2016-04-21 | |||
| US20170069481A1 | 2017-03-09 | |||
| US20180090624A1 | 2018-03-29 | |||
| JP2009015525A | 2009-01-22 | |||
| JPH0567634A | 1993-03-19 |
Attorney, Agent or Firm:
MAEDA & PARTNERS (JP)
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