Title:
SEMICONDUCTOR INTEGRATED-CIRCUIT DEVICE
Document Type and Number:
WIPO Patent Application WO/2024/047820
Kind Code:
A1
Abstract:
In an output circuit (11) included in IO cells (10), an M1 wiring line (32a) has been disposed between transistor arrays (24a, 24b) included in output transistors (P1), the M1 wiring line (32a) being connected to the gates of the transistors. M2 wiring lines (41) connected to the drains of the transistors have been provided to the transistor arrays (24a, 24b). The M1 wiring line (32a), in a plan view, is located between the M2 wiring lines (41) separated from each other. That is, in the plan view, the M2 wiring lines (41) connected to the drains of the transistors do not overlap the M1 wiring line (32a) connected to the gates of the transistors.
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Inventors:
TANAKA HIDETOSHI (JP)
Application Number:
PCT/JP2022/032871
Publication Date:
March 07, 2024
Filing Date:
August 31, 2022
Export Citation:
Assignee:
SOCIONEXT INC (JP)
International Classes:
H01L27/04; H01L21/82
Domestic Patent References:
| WO2021090688A1 | 2021-05-14 | |||
| WO2013038616A1 | 2013-03-21 | |||
| WO2018211931A1 | 2018-11-22 |
Foreign References:
| JP2007150150A | 2007-06-14 | |||
| JP2010147282A | 2010-07-01 | |||
| JP2013021249A | 2013-01-31 | |||
| JP2008244066A | 2008-10-09 |
Attorney, Agent or Firm:
MAEDA & PARTNERS (JP)
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