Title:
SEMICONDUCTOR MEMORY CIRCUIT AND DEVICE
Document Type and Number:
WIPO Patent Application WO/2013/105460
Kind Code:
A1
Abstract:
Provided is a semiconductor memory circuit comprising an oxide semiconductor insulated gate-type FET enabling increased performance without being affected by variance in threshold voltage. A semiconductor memory circuit (MC) is provided with: an insulated-gate FET first transistor element (T1) which is connected at the gate electrode to a memory node (N1), at the drain electrode to an intermediary node (N2), and at the source electrode to a data I/O terminal (DIO); an oxide semiconductor insulated-gate FET second transistor element (T2) which is connected at the gate electrode to a first control terminal (CIN1), at the drain electrode to the intermediary node (N2), and at the source electrode to the memory node (N1); a capacitive element (C1) connected at one terminal to the first voltage terminal (VIN1) and at the other terminal to the memory node (N1); and a switching element (S1) which, in accordance with the voltage level of at least the second control terminal (CIN2), controls the conduction state between the intermediary node (N2) and a second control terminal (CIN2), the second voltage terminal (VIN2) or the first voltage terminal (VIN1).
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Inventors:
YAMAUCHI YOSHIMITSU
Application Number:
PCT/JP2012/084025
Publication Date:
July 18, 2013
Filing Date:
December 28, 2012
Export Citation:
Assignee:
SHARP KK (JP)
YAMAUCHI YOSHIMITSU
YAMAUCHI YOSHIMITSU
International Classes:
G11C11/405; G11C11/56; H01L21/8242; H01L27/105; H01L27/108; H01L29/786
Foreign References:
| JP2011176294A | 2011-09-08 | |||
| JP2011123986A | 2011-06-23 | |||
| JP2011238334A | 2011-11-24 | |||
| JP2001351386A | 2001-12-21 |
Attorney, Agent or Firm:
MASAKI, YOSHIFUMI (JP)
Yoshifumi Masaki (JP)
Yoshifumi Masaki (JP)
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Claims: