Title:
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREFOR
Document Type and Number:
WIPO Patent Application WO/2023/060796
Kind Code:
A1
Abstract:
The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method therefor. The manufacturing method for the semiconductor structure comprises: providing a substrate having bitline contact areas; and forming a first conductive layer and a second conductive layer in each bitline contact area. According to the present disclosure, the first conductive layer and the second conductive layer are respectively formed by means of two deposition processes, and the concentration of doped impurities in the first conductive layer is lower than the concentration of doped impurities in the second conductive layer. Since the lower the concentration of the doped impurities, the higher the filling capacity, formation of a gap can be avoided during formation of the first conductive layer; moreover, since a contact hole formed by the first conductive layer in each bitline contact area has a small aspect ratio, during formation of the second conductive layer, formation of a gap in the second conductive layer can be avoided. Therefore, when a bitline and an isolation sidewall are subsequently formed, the isolation sidewall will not be damaged, electrical connection between a capacitor contact structure and the bitline will not be caused, and the yield of the semiconductor structure is improved.
Inventors:
YAN XUN (CN)
Application Number:
PCT/CN2022/071263
Publication Date:
April 20, 2023
Filing Date:
January 11, 2022
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
H01L21/8242; H01L27/108
Foreign References:
| CN113658918A | 2021-11-16 | |||
| CN108962894A | 2018-12-07 | |||
| CN103855002A | 2014-06-11 | |||
| CN113314469A | 2021-08-27 | |||
| JPH11176936A | 1999-07-02 |
Attorney, Agent or Firm:
LEADER PATENT & TRADEMARK FIRM (CN)
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