SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREFOR, AND MEMORY

WIPO Patent Application WO/2024/040645

A1

The embodiments of the present disclosure provide a semiconductor structure and a manufacturing method therefor, and a memory. The semiconductor structure comprises: a substrate; active pillars, which are located on a surface of the substrate, wherein the plurality of active pillars form an active pillar array having several columns arranged in a first direction and several rows arranged in a second direction, and each active pillar comprises a top active region, a channel region and a bottom active region, the first direction and the second direction intersecting and both being parallel to the surface of the substrate; word lines, which extend in the second direction, and cover the channel regions of the active pillars in the same column arranged in the first direction; a dielectric layer, which is located between the word lines and the active pillars, and covers at least a surface of the channel region; and bit lines, which extend in the first direction, and are electrically connected to the bottom active regions of the active pillars in the same row arranged in the second direction, wherein in the first direction, the size of the channel region is less than that of the top active region, and the size of the word lines does not exceed the sum of the size of the top active region and the size of the dielectric layer.

SHAO GUANGSU (CN)
XIAO DEYUAN (CN)

PCT/CN2022/118639

February 29, 2024

September 14, 2022

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CHANGXIN MEMORY TECH INC (CN)

H01L29/10

CN114141715A	2022-03-04
CN114141713A	2022-03-04
CN112185961A	2021-01-05
CN102034759A	2011-04-27
US20120119286A1	2012-05-17

CHINA PAT INTELLECTUAL PROPERTY OFFICE (CN)

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