SEMICONDUCTOR TEST DEVICE

WIPO Patent Application WO/2007/113940

A1

A computer (520) contains a test bench (521) for asynchronous simulation of the event driven method described in HDL. The description of the input of the test bench (521) is inputted to an LSI tester (510), converted to a signal input to a DUT (500), and applied to the DUT (500). After this, an output signal responded from the DUT is inputted to the LSI tester (510) and compared to an output signal obtained from a voltage condition table or the like for level judgment. The comparison result is inputted to the computer (520) and compared to an expectation value and output waveform data described in the HDL test bench (521) in the computer (520) so as to judge whether the DUT (500) is good. Accordingly, the LSI (DUT) can be tested under the same condition as the condition under which the LSI is actually used on a product.

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KODERA KEISUKE
MOTOHAMA MASAYUKI

PCT/JP2007/051380

October 11, 2007

January 29, 2007

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MATSUSHITA ELECTRIC IND CO LTD (JP)
KODERA KEISUKE
MOTOHAMA MASAYUKI

G01R31/3183; G01R31/28

JP2001067395A	2001-03-16
JP2003307543A	2003-10-31
JP2004252824A	2004-09-09
JPH09181590A	1997-07-11
JPH08114649A	1996-05-07
JP2005043274A	2005-02-17
JP2003222659A	2003-08-08

MAEDA, Hiroshi et al. (5-7 Hommachi 2-chome, Chuo-ku, Osaka-sh, Osaka 53, JP)

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