SEMICONDUCTOR WAFER, SEMICONDUCTOR DEVICE, POWER CONVERSION DEVICE, AND COOLING SYSTEM

WIPO Patent Application WO/2024/079780

A1

The purpose of the present invention is to provide a technology that is capable of suppressing the extension of a crack to the lower side of an interlayer insulating film when external stress associated with heat shrinkage stress is applied to a corner of a semiconductor element. A semiconductor wafer (1) is provided with a semiconductor substrate (10) in which an interlayer insulating film (9) and a surface protective film (8) covering the interlayer insulating film (9) are laminated atop the upper surface. A plurality of semiconductor elements (3), which are cut into small pieces by dicing along an opening (2a) formed in the surface protective film (8), are formed on the semiconductor substrate (10). The end of the interlayer insulating film (9) is set further back than the end of the surface protective film (8) in relation to the end of the semiconductor substrate (10) to be formed by dicing. In each of the diced semiconductor elements (3), the shape of the end of the interlayer insulating film (9) is set so that the distance Lx from the corner of the semiconductor substrate (10) to be formed by dicing to the end of the interlayer insulating film (9) and the thickness d of the semiconductor substrate (10) satisfy a relationship defined in expression 1.

JP4251915	Adhesive sheet
JP2000183219	MANUFACTURE OF IC PACKAGE
JPH0574931	MANUFACTURE OF INTEGRATED CIRCUIT WIRING BOARD

ATA YASUO (JP)
TANI MASAKAZU (JP)
TOI SHIGEO (JP)

PCT/JP2022/037823

April 18, 2024

October 11, 2022

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MITSUBISHI ELECTRIC CORP (JP)

H01L21/301

YOSHITAKE Hidetoshi et al. (JP)

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