The present invention relates to the field of programmable logic devices and in particular, but not exclusively, to a system and method for testing a reconfigurable logic array using a standard Automatic Test Pattern Generation (ATPG) tool.

ATPG tools allow manufacturers of logic circuits to distinguish between correct circuit behaviour and incorrect circuit behaviour caused by defects. In order to do this, ATPG tools analyse a model of the logic circuit to create pseudo-random sequences of data. These sequences, when fed to the logic circuits in question, create outputs which can be compared to expected output values. If these are differences between the expected and actual output values, such differences are associated with defects in the digital circuit.

When ATPG techniques are used to create sequences for reconfigurable logic circuits, a problem with this method can arise when inverting feedback loops are created by the random sequence of configuration data. Such inverting feedback loops are created when part of the logic device is configured in such a way that a signal can loop back on itself. If there is an even number of inverting elements in that loop, the state of all of the elements will find a steady state after the signal has completed the loop. On the other hand, if the loop contains an odd number of inverting elements, the loop will continue to oscillate indefinitely.

A further problem can occur when paths or loops being tested in the reconfigurable circuit have different path lengths. In such a case the propagation delay will vary depending on the length of the loop or path. This can lead to the propagation delay becoming greater than the length of the capture window or test cycle leading to incorrect values being determined by the ATPG tool.

In order to remedy this, some prior reconfigurable devices have found new ways of generating test patterns. These solutions however are specifically designed for particular reconfigurable devices having particular architectures. Accordingly, the test patterns generated by these solutions do not always conform to the ATPG used by the other components on a System on Chip (SoC). These devices are therefore not only costly in terms of computing resources, but also add significant complexity to the process for testing the larger Integrated Circuit (IC) of which the reconfigurable device forms a part of. Accordingly, there is a need for an improved system and method for eliminating the problems associated with variable propagation delay in reconfigurable devices during testing using standard Automatic Test Pattern Generators (ATPG).

In order to solve the problems associated with the prior art, the present invention provides a programmable logic device comprising a plurality of interconnected logic units arranged in an array, and blocking means arranged to apply a blocking mask for controlling signal propagation between the logic units during testing using an Automatic Test Pattern Generation (ATPG) tool.

A programmable logic device according to the first aspect has the advantage that signal propagation can be constrained by the blocking means so as to constrain propagation times to be within for example the capture window of a test ran by an ATPG tool.

Preferably, the blocking means is further operable to be controlled by an ATPG tool such that a blocking mask is repeatedly applied and for each repetition the blocking mask is arranged by the ATPG tool such that signal propagation is permitted a portion of the array that includes at least one logic unit that has not been tested by the ATPG tool in any previous iteration until all of a logic units in the portion of the array under test are tested by the ATPG tool. This allows the ATPG tool to obtain test coverage of a desired portion of the array.

Preferably, the blocking means comprises constraining means provided to each logic unit and operable to control signal propagation at least to or from the logic unit under test and preferably the blocking means further comprises a control circuit arranged to apply the blocking mask by controlling at least one of the constraining means.

In preferred embodiments, the blocking means further comprises a plurality of control memories each control memory being associated a logic unit under test, said control memories being operable to store configuration data for controlling the constraining means of the logic unit under test. Also, each associated constraining means is arranged to utilise the configuration data to control signal propagation.

In further preferred embodiments, the blocking means comprises a control circuit operable to apply the predetermined blocking mask by applying control signals directly to the constraining means of each logic unit. This permits the control circuit to provide direct control of the constraining means based on, for example, logic embodied by the circuit or data values read a memory. For example, preferably the blocking means further comprises a plurality of control memories each control memory being associated with a logic unit under test and operable to store configuration data such that the control circuit is operable to determine the configuration data stored in the control memories and apply control signals to the constraining means based on the configuration data.

Preferably, the control circuit is arranged to apply the blocking mask only according if the configuration data corresponds to one of a set of predetermined cases. Accordingly, an appropriate control circuit can prevent the application of illegal or undesirable blocking masks by an ATPG tool. Further preferably, the control circuit is further arranged to apply a default blocking mask that inhibits signal propagation in all logic units under test if the configuration data does not correspond to one the predetermined cases.

The blocking means preferably configures the array of logic units so that signals can only propagate within a group of adjacent logic units in the array.

In yet further preferred embodiments the blocking mask further configures the array of logic units so that the direction of signal propagation within the group of adjacent logic units is constrained.

Preferably, the constraining means comprises a multiplexer but it other preferred embodiments at least one of the constraining means comprises a pass-gate or at least one transistor.

Finally, it is preferred that the blocking means comprises logic circuitry implemented on programmable logic of the PLD. In a further aspect there is provided a method of configuring an array of logic units in a programmable logic device (PLD) in order to constrain signal propagation during testing using an Automatic Test Pattern Generation Tool, the method comprising the steps of, applying a blocking mask for controlling signal propagation between a group of logic units in the array, and testing the portion of the array to which the blocking mask has been applied.

In a yet further aspect there is provided a system for configuring an array of logic units in a programmable logic device in order to constrain signal propagation during testing, the system comprising, a programmable logic device according to the first aspect, and testing means arranged to test the portion of the array to which the blocking mask has been applied.

As will be appreciated, the present invention provides several advantages over the prior art. For example, because the present invention has the potential to modify the circuitry of the reconfigurable device, it is possible to use standard Automatic Test Pattern Generators (ATPG) to test the reconfigurable device.

Specific embodiments of the present invention will now be described with reference to the attached drawings, in which:

Figure 1 represents a reconfigurable device/fabric which can be used in conjunction with the present invention; the reconfigurable device/fabric is made up of a plurality of user programmable logic tiles;

Figure 2 represents a closer view of the reconfigurable device of Figure 1 , including Arithmetic Logic Units and switch boxes;

Figure 3a is functional block diagram of a portion of a simple reconfigurable device comprising a one dimensional array of tiles;

Figure 3b shows the functional components of a blocking circuit of a tile of the array of Figure 1 according to an embodiment of the present invention;

Figure 4a shows the reconfigurable device of Figure 3a when a simple blocking mask is applied to a first portion of the device;

Figure 4b shows the reconfigurable device of Figure 3a when a simple blocking mask is applied to a further portion of the device;

Figure 5 shows a portion of a reconfigurable device comprising sixteen tiles to which testing is to be applied together with a possible masking sequence in accordance with an embodiment of the invention; Figure 6 shows test state flops contained within two tiles of Figure 5 configured for a 'capture' and 'launch' tile;

Figure 7 shows a blocking circuit according to an embodiment of the present invention suitable for use with the tiles of Figure 5;

Figure 8a shows the functional components of four tiles of the programmable logic array of Figure 5 together with associated routing network components;

Figure 8b shows the four tiles of Figure 8a when the blocking mask has been applied to allow propagation in only the lower two tiles;

Figure 9 shows an alternative embodiment whereby combinatorial logic is utilised to control the blocking circuits of the 1 D array of tiles shown in Figure 3a.

Reconfigurable devices/fabrics, such as D-Fabrix (disclosed in, for example, US6353841 , US6252792, US2002/0157066) are commonly made up of a plurality of interconnected user programmable logic blocks or tiles, the fundamental building blocks of the system. This arrangement facilitates the use of an easily scalable configuration mechanism of equally regular structure.

Each user programmable tile is connected to a programmable routing network which can implement arbitrary connectivity between the tiles. Because each tile is connected to the routing network in the same way, the resulting device has a high degree of homogeneity. That is to say that, the way in which a specific subset of tiles of an array can be used and interconnected will be the same, regardless of where on the array that subset is located. Such a homogeneous array can be found disclosed in, for example, US6252792.

Figure 1 shows a diagram representing a programmable fabric 1 comprising a plurality of Logic Units (LUs) 2 interconnected by way of a plurality of switching sections 3. As shown in Figure 1 , each tile 20 is divided into four areas. A two-by-two group of LUs 2 and switching sections 3 forms a tile 20, which is the basic building block of the fabric, and is shown bounded by a thick line in Figures 1 and 2. Two of the areas, which are diagonally opposed in the tile 20, provide locations for a pair of LUs 2. The other two circuit areas, which are also diagonally opposed in the tile, provide the locations for a pair of switch boxes 3. Each LU can perform standard arithmetic operations (such as ADD, SUBTRACT) as well as standard logic operations (such as AND, NAND, OR, NOR) on a set number of bits. As will be appreciated by the skilled reader, some of the above functions will logically invert a signal, whilst other will not.

Figure 2 shows a closer view of the fabric 1 . Each tile 20 contains two LUs 2 and two switching sections 3. Each switching section 3 comprises a plurality of switches 7 which are each arranged to selectively connect a horizontal bus 1 1 to a vertical bus 12 at their intersection point. The horizontal and vertical buses can be any number of bits wide. Some switches 8, which are shown as black squares in Figure 2, are used for locally connecting the LUs 2 to the switching sections 3. Other switches 7, which are shown as striped squares in Figure 2, are used for longer distance connections (e.g. between switch sections 3).

As can be seen from Figure 1 and Figure 2, the fabric 1 has a high degree of homogeneity in that a particular tile can be used (i.e. configured or interconnected) in the exact same way as every other tile in the array.

First Embodiment

Figure 3a shows a simple embodiment of the present invention in which a reconfigurable device has a logic array in one dimension only. As will be appreciated by a person skilled in the art, Figure 3a is a simplified diagram representing a portion of a reconfigurable device forming part of an area for test, and is merely used to illustrate an embodiment of the present invention. The structure and functionality of the circuits shown in the figures are not to be interpreted as limiting to the functionality of the present invention.

The portion of the logic array shown in Figure 3a comprises four logic blocks 31 , 32, 33 and 34 comprising a logic unit ('LOGIC') 31 -1 , 32-1 , 33-1 , 34- 1 , input blocking circuit 31 -3, 32-3, 33-3, 34-3, and output blocking circuit 31 -4, 32-4, 33-4, 34-4. As will be appreciated by the skilled reader, the logic units 31 - 1 , 32-1 , 33-1 , 34-1 can be equated with the logic units 2 of Figures 1 and 2 Intra-routing is represented by routing blocks 31 -2, 32-2, 33-2, 34-2 interconnected between the logic units 31 -1 , 32-1 , 33-1 , 34-1 and the input and output blocking circuits 31 -3, 32-3, 33-3, 34-3 and 31 -4, 32-4, 33-4, 34-4. The intra-routing 31 -2, 32-2, 33-2, 34-2 can be equated with the switching sections 3 of Figure 2 although as will be appreciated the exact architecture may vary depending on the design parameters of the logic array.

In addition, such a device may also comprise further routing circuitry, providing for example an overlying routing network for routing signals between tiles. However, any overlying routing network has been omitted in this embodiment in order for ease of understanding of the underlying principles of the invention.

The logic array also comprises a masking control logic 600 which together with blocking circuits 31 -3, 32-3, 33-3, 34-3 and 31 -4, 32-4, 33-4, 34-4 controls the propagation of signals to and from the tile.

The masking control logic 600 comprises logic circuitry arranged to apply a set of predetermined rules which control the propagation between tiles 31 , 32, 33, and 34 at each test cycle. Typically the state of the blocking circuits for a particular logic unit will be dependent on the configuration of neighbouring tiles. In an embodiment the masking circuit 600 itself may be reconfigurable and configuration of the masking circuit implemented at test.

Outputs of the masking logic 600 are connected to respective blocking circuits 31 -3, 32-3, 33-3, 34-3 and 31-4, 32-4, 33-4, 34-4 such that the masking logic can control the behaviour during test. Each tile 31 , 32, 33, and 34 has a set of registers or test state flops (TSF) 31 -5, 32-5, 33-5, 34-5 that are configurable by the ATPG tool at test. Each TSF 31 -5, 32-5, 33-5, 34-5 in this embodiment is formed as part of the device fabric separate to the logic units 31 - 1 , 32-1 , 33-1 , 34-1 however it is also possible that the TSFs 31-5, 32-5, 33-5, 34- 5 could comprise registers forming part of configuration memories (not shown) of the tiles 31 , 32, 33 and 34. The rules encapsulated by the masking logic apply the blocking mask depending on the values stored in the TSFs 31 -5, 32-5, 33-5, 34-5 by the ATPG tool.

Each tile may be configured by the masking logic in one of a plurality of blocking states of the blocking circuits 31 -3, 32-3, 33-3, 34-3 and 31 -4, 32-4, 33- 4, 34-4 depending on the value stored in the corresponding TSF 31 -5, 32-5, 33-

5, 34-5.

For example, these blocking states could comprise one of:

a 'launch' state whereby output blocking circuit 31 -4, 32-4, 33-4, 34-4 is controlled by the masking logic to allow outputs to propagate from the tile but input blocking circuit 31 -3, 32-3, 33-3, 34-3 is controlled by the masking logic so that inputs are blocked;

a 'routing' state whereby input and output blocking circuits 31 -3, 32-3, 33-3, 34-3 and 31 -4, 32-4, 33-4, 34-4 are both controlled by the masking logic so that inputs and outputs are allowed to propagate;

a 'capture' state whereby input blocking circuit 31 -3, 32-3, 33-3, 34-3 is controlled by the masking logic to allow inputs to propagate but blocking circuit 31 -4, 32-4, 33-4, 34-4 is controlled so that outputs are blocked; or

an 'isolation' state where a tile is isolated from adjacent tiles in the sense that both blocking circuits 31 -3, 32-3, 33-3, 34-3 and 31 -4, 32-4, 33-4, 34-4 are controlled by the masking logic to block signal propagation so that inputs and outputs are blocked.

To encode these states requires at least two bits. For example the four states could be encoded as L=00, R=01 , C= 10, 1= 1 1 . Accordingly, the TSFs 31 -5, 32-5, 33-5 and 34-5 comprise two flip-flops to store the state information.

The state of a tile is configured by the ATPG tool during test and the masking logic ensures that only cases according to rules encapsulated by the masking logic can occur.

The possible masking configurations that can be implemented by the masking logic in this embodiment are set out in the following table.

TABLE 1. State decode cases of 1D array with 4 TSF states Where L = launch state, C= capture state, R = routing state and I = isolation state.

These are the only configurations that will be recognised by the masking logic and all others will result in defaulting to the isolation state. For example, in implementing case 1 the rule embodied in the logic could be expressed in pseudo code as: if (TSF 31 -5=00 and TSF 32-5=01 and TSF 33-5= 10 and

TSF 34-5= 11 )

then set input blocking circuit 31 -3 to blocking state and output blocking circuit 31 -4 to non-blocking state;

set input and output blocking circuits 32-3 and 32-4 to non-blocking state;

set input blocking circuit 33-3 to non-blocking state and output blocking circuit 33-4 to blocking state;

set input and output blocking circuits 34-3 and 34-4 to blocking state

endif.

Similar rules are implemented for the other allowed cases. If an arrangement of states is encountered by the masking logic that is not recognised (e.g. two consecutive launch or capture tiles) then it will default to a default case where all the tiles are placed in an isolation state. Thus, by manipulating the values in the TSFs, the ATPG tool can usefully control signal propagation during each test iteration.

Turning to figure 3b one possible implantation of the blocking circuits 31- 3, 32-3, 33-3, 34-3 and 31 -4, 32-4, 33-4, 34-4 is shown comprising a multiplexer 46 where a selection input of the multiplexer is provided with a control value from the masking logic. The control values are determined at test by the masking circuit 600 in accordance with the TSF values of each tile. One input of the multiplexer 46 is connected to the logic unit 31 -1 , 32-1 , 33-1 , 34-1 and the other input of the multiplexer 46 is set to 'X' which as will be appreciated denotes the connection being physically unconnected. Depending on the design tool utilised a connection that is unconnected can be designated as an or a Ό'.

Thus, the output of the multiplexer 45 will default to the 'X' value unless the associated register contains a binary 1 value in which case the signal to or from the logic unit will be permitted to propagate. It should be noted that in this embodiment signal propagation is possible in one direction only across the 1 -D array, however, as will be appreciated the invention is equally applicable to arrays where signal propagation is possible in both directions in the 1 -D array. Further, as will be explained further below in connection with the second embodiment, application of the invention to arrays of logic having two (or more) dimensions is also envisaged.

Turning now to Figure 4a the circuit during a first test iteration is shown where a blocking mask is applied to a portion of a logic array comprising tiles 31 , 32, 33 and 34. The selected blocking mask comprises configuration data applied to the TSFs 31 -5, 32-5, 33-5, 34-5 for masking all but a row of three horizontally adjacent tiles and has been applied during a first testing iteration to block all but tiles 31 , 32 and 33. As shown, the ATPG tool applies mask by configuring the values of the TSFs 31 -5, 32-5, 33-5, 34-5 so that input blocking circuit 31 -3 and output blocking circuit 31 -2 of tile 31 are set to 0 and 1 ('off' and 'on') respectively by the masking logic (not shown). For tile 32 the registers controlling the input and output blocking circuits 32-3 and 32-4 are both set to 1 (both 'on'). Tile 33 mirrors tile 31 so that the registers controlling the input and output blocking circuits 33-3 and 33-4 are set to 1 and 0 ('on' and Off') respectively. All other tiles in the device have their registers set to 0 ('off') so that no data can flow into or out of those tiles. In this way the logic array is constrained during the test iteration such that no data is allowed to propagate into the first tile 32 from tiles outside of the masked portion and no data is allowed to propagate from the output of tile 33 to tiles outside of the masked portion. Thus with the mask applied signals propagate from tile 31 through tile 32 and ending at tile 33, or from tile 31 ending at tile 32, or from tile 32 ending at tile 33. The propagation time is therefore controlled in view of the predictable number of logic units through which a signal can travel in the un-masked region.

In Figure 4b the testing operation enters a new testing iteration in which a mask is applied to block all but tiles 32, 33 and 34. The bit sequence 0,1 ,1 ,1 ,1 ,0 ('off', 'on', 'on', On', On', Off' is applied to the respective blocking circuits 32-3, 32-4, 33-3, 33-4, 34-3, 34-4 by the masking logic after appropriate configuration of the associated TSFs (TSF 32-5=Ό0', TSF 33-5=Ό1 ' and TSF 34-5='10' respectively). Again, the rest of the tiles are masked by the ATPG tool by configuration of their respective registers such that no data can propagate into or out of those tiles. Testing proceeds on the masked circuit with patterns of test values applied to the masked portion. The mask is then moved again and a further test iteration is performed. This continues until the repeatedly applied mask has covered all of the tiles in the 1 D array at least once during testing. In this way all of the logic units in the reconfigurable device are tested in a constrained and predictable way so that unpredictable propagation times do not have a detrimental effect on the testing process.

Second Embodiment

A further embodiment of the present invention is shown in Figure 5 which is a representation of a reconfigurable device having an array of logic units 500. The illustrated portion of the reconfigurable device comprises 16 tiles arranged in a 4x4 array. Figure 8a shows the functional components of the 4 tiles 51 , 52, 53 and 54 in the upper left quadrant of the array in more detail. As shown each tile 51 , 52, 53 and 54 comprises a logic unit 51 -1 , 52-1 , 53-1 , 54-1 , a set of associated TSFs 51 -2, 52-2, 53-2, 54-2 and blocking circuits 51 -3, 52-3, 53-3, 54-3. In this embodiment, the logic units 51 -1 , 52-1 , 53-1 , 54-1 can be equated with the logic units (LUs) 2 as per Figures 1 and 2 already described above. The blocking circuits 51-3, 52-3, 53-3, 54-3 are operable to control signal propagation to and from the logic blocks 51 -1 , 52-1 , 53-1 , 54-1 respectively based on signals from a masking circuit 600. Each blocking circuit 51 -3, 52-3, 53-3, 54-3 can be configured to allow outputs from the logic unit to propagate or to allow input signals to its respective logic unit to propagate. In this embodiment signal propagation is controlled by applying a mask that isolates signal propagation in all but two adjacent tiles. In accordance with the nomenclature used to describe the first embodiment, the two un-masked tiles are designated as launch and capture tiles respectively. This labelling denotes the nominal direction of signal propagation i.e. signals travel from a 'launch' tile to a 'capture' tile.

The designation of launch tile and capture tiles is performed by of the ATPG tool loading data into TSFs 51 -4, 52-4, 53-4, 54-4. Like the first embodiment described above the TSFs 51 -4, 52-4, 53-4, 54-4 are preferably loaded via a scan chain and can be independent from or form part of a configuration memory. Although not shown in Figures 5 or 8a the 2D array also has an associated a masking configuration circuit which is arranged to read the values stored in TSFs 51 -4, 52-4, 53-4, 54-4 and provide appropriate signals to the blocking circuits 51 -3, 52-3, 53-3 and 54-3.

The masking concept is illustrated in figure 6 which shows two arbitrary adjacent tiles 61 and 62 of a logic array such as that shown in Figure 5 each tile having TSFs 61 -1 , 62-1 and 61 -2, 62-2 respectively. Using the same notation and assuming the same possible states as the first embodiment, the first tile 61 is designated as a capture tile by the ATPG tool by loading TSFs 61 -1 and 61 -2 with a Ί Ο'. Similarly, the second tile 72 is configured as a launch tile by loading TSFs 62-1 and 62-2 with ΌΟ'.

An embodiment is shown in figure 7 wherein blocking circuits are controlled by signals from the masking circuit. The masking circuit 600 is arranged as in the first embodiment to read the TSF values and generate appropriate control signals provided the TSF values are valid. The blocking circuit comprises an output multiplexer 71 for controlling signal propagation out of a corresponding logic unit and an input multiplexer 72 controls signal propagation into the corresponding logic unit. The selection bits of the output and input multiplexers 71 and 72 are connected to outputs of the masking circuit. When tile is set to a launch state then the masking circuit sets the selection bit of the output multiplexer to '1 ' and the selection bit of the input multiplexer to '0' so that signal propagation is permitted out of but not into the logic unit. However, if the tile is set to the capture state then the masking circuit provides a selection bit value of Ό' to the output multiplexer and a selection bit value of Ί ' to the input multiplexer so that signal propagation is permitted to but not from the logic unit.

The logic units of the reconfigurable device are connected by a routing network comprising nodes and connections which under normal operation permit tiles to transmit and receive signals between each other. Each logic unit is typically connected to at least one node of the routing network. Four nodes 55 to 58 of the routing network associated with respective logic units 51 -1 , 52-1 , 53-1 , 54-1 are shown in Figure 8a. The combination of a logic unit 51 -1 , 52-1 ,

53- 1 , 54-1 and a corresponding routing node 55 to 58 comprise tiles 51 to 54 whereby the routing node 55 to 58 can be equated with a switching section 3 as per figures 1 and 2.

Each node of the routing network 55 to 58 is arranged so that it can receive or transmit data to and from a corresponding logic unit 51-1 , 52-1 , 53-1 ,

54- 1. Each node 55 to 58 has four input/output ports suitable for connection to other adjacent nodes of the routing network.. Each routing node 55 to 58 also comprises four blocking circuits 55n, 55s, 55w, 55e each connected to a respective input/output port. Signal propagation to and from the upper, lower, left and right ports of each node is controlled by the four respective blocking circuits 55n, 55s, 55w, 55e. This arrangement allows the masking circuit to control the transmission and reception of signals from the four nodes 55 to 58 in addition to the corresponding logic units 51-1 , 52-1 , 53-1 , 54-1 . For example, node 55 is associated with logic unit 51 -1 and has its right port 55e connected to a left port 57w of routing network node 57. Further, its lower port 55s is connected to the upper port 56n of routing network node 56. These additional connections provide potential signal propagation paths from logic unit 51 -1 to logic unit 52-1 and logic unit 53-1 respectively (associated with respective nodes 56 and 57). As shown, similar connections are made for the other logic units 52-1 , 53-1 , 54-1 and their respective nodes 56, 57, 58. A method of testing the circuit using an ATPG tool will now be explained in detail with reference to figures 8a and 8b. In this embodiment a launch- capture mask comprising two un-masked tiles is effectively 'stamped' (or in other words, 'applied') to the logic array such that data can only propagate from the launch tile 53 to capture tile 51 . Applying the launch-capture mask requires the ATPG tool to configure the TSFs so that the blocking circuits 51-3 and 55n, 55s, 55w, 55e and 53-3 and 57n, 57s, 57w and 57e to constrain signal propagation accordingly. To accomplish this, the value of the TSF 53-4 of tile 53 is loaded with the launch state '00' . The masking control circuit reads the TSF value and sends appropriate control signals to the blocking circuits so that the blocking circuit 53-3 of tile 51 and left-most blocking circuit 57w of node 57 are configured to allow output signals but not input signals. Similarly, the TSF 51 -4 of tile 51 is loaded with the capture state '01 '. The masking control circuit reads the TSF value and sends appropriately configured control signals to the blocking circuits so that the blocking circuits 51 -3 of tile 51 and the right-most blocking circuit 55e of node 55 to allow input signals but not output signals. All other TSFs in the array are loaded with the isolate state '1 1 ' by the ATPG tool. Accordingly, the array is now configured so that signals are permitted to propagate only along a path starting at logic unit 53-1 through the routing network via node 57 to node 55 and ending at logic unit 51 -1 . As will be appreciated by constraining the behaviour of the array in this manner it restricts the likely propagation time such that test failure as a result of the test time exceeding the capture window is less likely.

Figure 8b shows a further test iteration whereby the ATPG tool reconfigures the TSFs 51 -4, 52-4, 53-4, 54-4 so that the masking circuit isolates all but tiles 52 and 54. Accordingly, tile 52 becomes the capture tile and tile 54 becomes the launch tile. The ATPG tool configures TSFs 52-4 and 54-4 of the tiles 52 and 54 to capture and launch states '10' and '00' respectively in an analogous manner to the above described iteration. Accordingly, in this iteration the array is now configured so that signals are permitted to propagate only along a path starting at logic unit 54-1 through the routing network via node 58 and node 56 to end at logic unit 52-1 . Further test iterations are performed by the ATPG tool until the ATPG tool is satisfied that all the tiles in the portion of the array under test have been tested at least once. A possible sequence in which the blocking mask could be applied across the logic array is shown in Figure 5. Each dotted rectangle 501 to 512 represents a launch-capture pair of a mask applied in an iteration of the testing procedure performed by the ATPG. The launch-capture tiles in which signals are allowed to propagate are within the dotted perimeter of the rectangle. As shown, in this embodiment at least 12 iterations would be required by an ATPG tool to test all 16 tiles of the portion of the array under test utilising a simple launch capture pair. In certain circumstances where the logic array is large or non-homogenous the ATPG tool may partition the logic array into portions and perform the above described test process to each portion. This permits different test patterns to be applied to each portion as necessary.

Alternative embodiments

In the above embodiment the selection signals that are provided to control the input and output multiplexers are control signals from a masking control circuit 600, however, in other embodiments the MUXs may receive control data directly from the TSFs. An embodiment is shown in Figure 9 of such an arrangement when applied to the first embodiment of figure 3a. As shown, instead of having the masking circuit 600 to the blocking circuits, outputs of the TSFs are connected directly to the blocking circuits (e.g. to the selection inputs of corresponding MUXs). The blocking circuits are therefore able to perform a sequence of masking iterations where patterns of TSF data are loaded by the ATPG tool. This embodiment permits a simpler implementation but at the cost that there is no masking control circuit to limit the possible states applied to the blocking circuits. Instead the ATPG tool is relied upon not to load TSF data by ATPG tool constraints corresponding to illegal configurations.

Further, in the above embodiments the masking pattern comprises a plurality of horizontally adjacent tiles in which signal propagation is permitted while the rest of the array tiles are placed in an isolated state. However, in further embodiments the masking pattern could comprise other patterns of adjacent tiles such as vertically adjacent tiles or a combination of horizontal and vertical tiles (e.g. a cross or L-shape). The shape and size of the masking pattern may be selected by the ATPG tool automatically based on the test criteria (e.g. number of iterations, permitted propagation length) and to provide an efficient fit with respect to the shape and dimensions of the logic array to be tested.

In the second embodiment described above the blocking circuits can be designated as a launch or capture tile, however, in further embodiments they could be applied a third designation as a 'routing tile' in a similar manner to the first embodiment by loading the TSF of the tile with an appropriate configuration value. For example, in a non-masked region of three tiles the routing node of the middle tile could be configured by the masking circuit (based on having a routing state loaded in its TSF) to allow signals from the launch tile to propagate though the routing tile to the capture tile while denying any propagation to and from the logic unit in the routing tile. Alternatively, propagation could also be permitted through the logic unit of the routing tile.

In the above embodiments the connections between logic units and routing nodes comprised single inputs/outputs however in further embodiments they may comprise multiple inputs and outputs. This could give rise to the need for multiple capture, routing and launch states where differing states permit propagation of different numbers of the inputs and outputs from a tile. As each state has a unique value for storage in the TSFs then if we have M=sum(L states) + sum(R states) + sum(C states) +1 (1 state) states then we will need K= [log ₂ M] bits to encode them, assuming we use binary encoding. Accordingly each TSF will comprise K flops. So if we assume we have L1 , L2, R1 , R2, R3, C1 , C2, I then the number of states is 8 and we need 3 bits to encode these states. For example, L1 =000, L2=001 , R1 =010, R2=011 , R3= 100, C1 = 101 , C2=1 10 and 1=1 11 . Taking the first embodiment as an example, the masking control circuit could ensure that only the following cases are permitted. If for example each tile had two input/outputs then C1 might permit inputs from one of those connections while C2 permitted inputs to be received from both. In another example, R1 could permit propagation from the first input/output only, R2 from the second input/output only and R3 from both. As will be appreciated other permutations could be chosen depending on the characteristics of the array and testing to be performed using the ATPG tool.

TABLE 2. State decode cases of 10 array with 8 TSF states

The masking control circuit would implement rules in a similar manner to the first embodiment so that only the cases set out in the table were permitted otherwise the masking control circuit would default to the inhibit all case.

Throughout the description the term blocking mask is used to describe configuration of a circuit than can disconnect logic blocks in an array from each other or configuration of any other means to inhibit signal propagation. In the embodiments above the signal propagation is controlled by blocking circuits comprising UXs. However, as will be appreciated by the skilled reader other equivalent logic circuit combinations or other electronic circuit could be utilised having equivalent functionality. For example, appropriately configurable pass- gates could be utilised to connect or disconnect logic blocks in a programmable device. Similarly, other combinations of transistors could be used. As will be appreciated, the means for applying the blocking mask is not limited to these examples.