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Title:
SOLID-STATE IMAGING APPARATUS AND METHOD FOR MANUFACTURING SAME, AND ELECTRONIC INFORMATION APPARATUS
Document Type and Number:
WIPO Patent Application WO/2008/018329
Kind Code:
A1
Abstract:
A high performance solid-state imaging apparatus is manufactured by correctly controlling the thickness of a reflection preventing film arranged on the surface of a photodiode and the thickness of a side wall arranged on a gate electrode side wall of a MOS transistor, without increasing the number of manufacturing steps. In the solid-state imaging apparatus (10) wherein a plurality of photodiodes in an imaging region and each MOS transistor in the peripheral circuit region are mixedly mounted, the reflection preventing film (7) on the surface of the photodiode and the side wall (9) arranged on the side wall of the gate electrode (3) of the MOS transistor are formed at the same time in the same step by laminating three layers of insulating films (4-6) and by employing photography and dry etching. Specifically, the reflection preventing film (7) controls the refractive indexes and the thicknesses of the lower layer insulating film (3) and the middle layer insulating film (4) to be optimum so that reflection preventing effects are high, and the side wall (9) controls the thicknesses of the lower insulating film (4), the middle layer insulating film (5) and the upper layer insulating film (6) to be optimum so that an LDD region can be accurately formed.

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Inventors:
KAWANO HIROYUKI
Application Number:
PCT/JP2007/065022
Publication Date:
February 14, 2008
Filing Date:
July 31, 2007
Export Citation:
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Assignee:
SHARP KK (JP)
KAWANO HIROYUKI
International Classes:
H01L27/14; H04N5/335; H04N5/369; H04N5/372; H04N5/374; H04N101/00
Foreign References:
JP2001245439A2001-09-07
JP2004335588A2004-11-25
JP2005340475A2005-12-08
JPH0396421A1991-04-22
Attorney, Agent or Firm:
YAMAMOTO, Shusaku et al. (Crystal Tower2-27, Shiromi 1-chome Chuo-ku,Osaka-shi, Osaka 15, JP)
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