Title:
SOLID-STATE IMAGING ELEMENT, MANUFACTURING METHOD, AND ELECTRONIC DEVICE
Document Type and Number:
WIPO Patent Application WO/2018/047635
Kind Code:
A1
Abstract:
The present disclosure relates to a solid-state imaging element, a manufacturing method, and an electronic device which make it possible to further reduce chip size. The solid-state imaging element includes: a semiconductor substrate on which a pixel region where a plurality of pixels are arranged in a plane is provided; a wiring layer which is laminated on the semiconductor substrate and in which wiring connected to the plurality of pixels is provided; and a support substrate which is bonded to the wiring layer and supports the semiconductor substrate. A plurality of electrode pads used for electrically connecting to the outside are arranged in the wiring layer at positions overlapping the pixel region in a plan view of the semiconductor substrate, and through-holes are provided in the support substrate at locations corresponding to the plurality of electrode pads. The present art can be applied to a back-illuminated CMOS image sensor in a wafer-level CSP, for example.
Inventors:
KOMAI NAOKI (JP)
Application Number:
PCT/JP2017/030463
Publication Date:
March 15, 2018
Filing Date:
August 25, 2017
Export Citation:
Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
H01L23/12; H01L27/146; H04N5/369
Foreign References:
| JP2015126187A | 2015-07-06 | |||
| JP2009277732A | 2009-11-26 | |||
| JP2010273757A | 2010-12-09 | |||
| JP2014099436A | 2014-05-29 |
Attorney, Agent or Firm:
NISHIKAWA Takashi et al. (JP)
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