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Title:
SOLID-STATE IMAGING ELEMENT, MANUFACTURING METHOD, AND ELECTRONIC APPARATUS
Document Type and Number:
WIPO Patent Application WO/2023/153300
Kind Code:
A1
Abstract:
The present disclosure pertains to a solid-state imaging element, a manufacturing method, and an electronic apparatus which make it possible to achieve higher performance. In this solid-state imaging element, a first semiconductor substrate, in which photodiodes and some pixel transistors are provided for respective pixels, has bonded thereto a second semiconductor substrate in which other pixel transistors excluding the some pixel transistors making up the pixels are provided. An interlayer film is layered, with an insulating film therebetween, onto a surface of the second semiconductor substrate that is the opposite side from the surface of the side where the first semiconductor substrate is bonded. A through electrode that penetrates the second semiconductor substrate from the interlayer film side and is electrically connected to the first semiconductor substrate is provided. The through electrode is made up of a lower-stage electrode provided going from substantially the same height as the interlayer film-side surface of the second semiconductor substrate toward the second semiconductor substrate, and an upper-stage electrode that penetrates the interlayer film and is connected to the lower-stage electrode. The present art can be applied to, for example, to back-surface illuminated CMOS image sensors of a laminated structure.

Inventors:
KITAMURA SHOTA (JP)
Application Number:
PCT/JP2023/003341
Publication Date:
August 17, 2023
Filing Date:
February 02, 2023
Export Citation:
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Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
H01L27/146; H01L21/3205; H01L21/768; H01L23/522; H01L23/532; H01L25/065; H01L25/07; H01L25/18; H04N25/76
Domestic Patent References:
WO2019131965A12019-07-04
WO2018180575A12018-10-04
Foreign References:
JP2013201188A2013-10-03
Attorney, Agent or Firm:
NISHIKAWA Takashi et al. (JP)
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