Title:
SOLID-STATE IMAGING ELEMENT
Document Type and Number:
WIPO Patent Application WO/2023/007772
Kind Code:
A1
Abstract:
The present invention improves the image quality of a solid-state imaging element in which all pixels are simultaneously exposed to light. An upstream circuit generates, in the following order, a prescribed reset level and a signal level that corresponds to an exposure amount, and holds the same in first and second capacitive elements, respectively. A selection circuit performs, in the following order, a control for connecting one of the first and second capacitive elements to a prescribed downstream node, a control for disconnecting both the first and second capacitive elements from the downstream node, and a control for connecting the other of the first and second capacitive elements to the downstream node. A downstream reset transistor initializes the level of the downstream node when both the first and second capacitive elements have been disconnected from the downstream node. A downstream circuit reads, in the following order, the reset level and the signal level from the first and second capacitive elements via the downstream node, and outputs the same.
Inventors:
TAMAKI RYO (JP)
Application Number:
PCT/JP2022/003521
Publication Date:
February 02, 2023
Filing Date:
January 31, 2022
Export Citation:
Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
H01L27/146
Domestic Patent References:
| WO2013084408A1 | 2013-06-13 |
Foreign References:
| JP2019057873A | 2019-04-11 | |||
| JP2009038772A | 2009-02-19 |
Attorney, Agent or Firm:
MARUSHIMA, Toshikazu (JP)
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