STORAGE BLOCK AND MEMORY

WIPO Patent Application WO/2023/115849

A1

A storage block and a memory, relating to the technical field of semiconductors. The storage block comprises: a plurality of storage arrays (101) arranged along a first direction and used for storing data and check codes, each storage array being divided into at least two array units (110); a plurality of read-write control circuits (102) in one-to-one correspondence to the storage arrays and used for writing the data and check codes to or reading the data and check codes from the corresponding storage arrays, the read-write control circuits being electrically connected to the array units by means of different data signal lines and configured to only access one array unit in the corresponding storage arrays at one time; and a plurality of error checking and correction units (103) electrically connected to the plurality of read-write control circuits and used for performing error checking and/or correction on the data according to the check codes, wherein during a read operation, data and check codes read by each read-write control circuit are divided into at least two parts, and the read-write control circuit is configured to transmit each part to different error checking and correction units.

JP2003150460	MEMORY INITIAL ACTIVATION CONTROL CIRCUIT
WO/2021/138125	APPARATUSES, SYSTEMS, AND METHODS FOR ERROR CORRECTION
JP2008198330	SEMICONDUCTOR MEMORY DEVICE FOR BYTE-BASED MASKING OPERATION AND METHOD OF GENERATING PARITY DATA

SHANG WEIBING (CN)
LI HONGWEN (CN)

PCT/CN2022/099559

June 29, 2023

June 17, 2022

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CHANGXIN MEMORY TECH INC (CN)

G11C29/42

CN213183603U	2021-05-11
CN107767919A	2018-03-06
CN113140252A	2021-07-20
CN1421871A	2003-06-04
US20190229753A1	2019-07-25

BOXIN CHINA INTELLECTUAL PROPERTY (CN)

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