FIELD AND BACKGROUND OF THE DISCLOSURE

The present disclosure, in some embodiments thereof, relates to communication systems designed for enabling transfer of digital data from a transmitter to a receiver. More specifically, but not exclusively, the present disclosure relates to a system and method for retransmission of incorrectly received data, namely data which was detected or decoded with errors by the receiver.

In communication systems, Automatic Repeat Request (ARQ) protocol is a known error correction protocol, where in case a transmitted packet was incorrectly decoded by a receiver, the receiver discards the incorrect data carried by the received packet (as well as any intermediate results generated while processing that packet), and the transmitter retransmits the packet to the receiver. The receiver then attempts to decode the retransmitted packet independently of the previous incorrectly received packet. Hybrid ARQ (HARQ) is a more sophisticated method combining Forward Error Correction (FEC) code and ARQ error control. In HARQ, soft combining of Log Likelihood Ratio (LLR) metrics (or combining of equalized symbols) from different retransmitted/transmitted versions of the same data is carried out at the receiver. This implies that the LLR metrics (or equalized symbols) respective to incorrectly decoded packets are stored in the memory of the receiver and are combined with LLR metrics extracted from retransmissions of the same information, increasing the probability for correct data detection (after retransmission).

The improved performance (after combining) leads to higher throughput and lower latency - due to a reduced number of retransmissions and/or higher spectral efficiency due to higher Modulation and Coding Scheme (MCS) being used.

SUMMARY OF THE DISCLOSURE

It is an object of the present disclosure to describe a system and a method of HARQ in which only information bits out of the data which was incorrectly received are being retransmitted, without the accompanying redundancy (or parity) bits, which were attached to the information bits upon first transmission of the data. The foregoing and other objects are achieved by the features of the independent claims. Further implementation forms are apparent from the dependent claims, the description and the figures.

In one aspect, the disclosure relates to a method of sending information from a transmitter to a receiver, comprising: sending, by the transmitter, a first signal, the first signal carrying a first sequence of symbols, the first sequence of symbols representing a first bit sequence of length M _x , the first bit sequence comprising N ₁ information bits and (M ₁ — /V _x ) redundancy bits, wherein 1 < N ₁ < M and the N _t information bits represent a piece of information; receiving, by the receiver, the first signal; generating, by the receiver, a reconstructed first sequence of symbols by demodulating the received first signal; generating, by the receiver, a first sequence of Log Likelihood Ratio, LLR, metrics, of length M _x , by generating for each symbol of the reconstructed first sequence of symbols one or more LLR metrics; generating, by the receiver, a reconstructed first bit sequence of length M _x , based on the first sequence of LLR metrics; determining, by the receiver, that the reconstructed first bit sequence is invalid; sending, by the receiver, a request; receiving, by the transmitter, the request; sending, by the transmitter, a second signal in response to the received request, the second signal carrying a second sequence of symbols, the second sequence of symbols representing a second bit sequence of length iV ₂ , the second bit sequence comprising N ₂ information bits out of the N ₁ information bits of the first bit sequence and not comprising any redundancy bits, wherein 1 < N ₂ receiving, by the receiver, the second signal; generating, by the receiver, a reconstructed second sequence of symbols by demodulating the received second signal; generating, by the receiver, a second sequence of LLR metrics, of length N ₂ , by generating for each symbol of the reconstructed second sequence of symbols one or more LLR metrics; generating, by the receiver, a consolidated sequence of LLR metrics, of length M _x , wherein generating the consolidated sequence of LLR metrics comprises merging the first sequence of LLR metrics and the second sequence of LLR metrics; and generating, by the receiver, a second reconstructed first bit sequence of length M based on the consolidated sequence of LLR metrics.

In a first possible implementation of the method of the first aspect, the second bit sequence comprises all information bits from the first bit sequence.

In a second possible implementation of the method of the first aspect, the second bit sequence comprises less than all information bits from the first bit sequence.

In a third possible implementation of the method of any one of the preceding implementations, determining that the reconstructed first bit sequence is invalid comprises or consists in determining that a syndrome of the reconstructed first bit sequence is a fault syndrome.

In a fourth possible implementation of the method of any one of the preceding implementations, the first bit sequence is a codeword of a Forward Error Correction, FEC, code.

In a fifth possible implementation of the method of the fourth implementation, determining that the reconstructed first bit sequence is invalid comprises or consists in determining that the reconstructed first bit sequence is not a valid codeword of the FEC code.

In a sixth possible implementation of the method of any one of the preceding implementations, generating the consolidated sequence of LLR metrics comprises adding to each of JV ₂ metrics out of the M metrics of the first sequence of LLR metrics a value of one of the JV ₂ metrics of the second sequence of LLR metrics.

In a seventh possible implementation of the method of any one of the preceding implementations, the consolidated sequence of LLR metrics is a first consolidated sequence of LLR metrics and the method further comprises: determining, by the receiver, that the second reconstructed first bit sequence is invalid; sending, by the receiver, a second request; receiving, by the transmitter, the second request; sending, by the transmitter, a third signal in response to the received second request, the third signal carrying a third sequence of symbols, the third sequence of symbols representing a third bit sequence of length M ₃ , the third bit sequence comprising M ₃ bits from the first bit sequence, wherein 1 < M ₃ < M _x ; receiving, by the receiver, the third signal; generating, by the receiver, a reconstructed third sequence of symbols by demodulating the received third signal; generating, by the receiver, a third sequence of LLR metrics, of length M ₃ , by generating for each symbol of the reconstructed third sequence of symbols one or more LLR metrics; generating, by the receiver, a second consolidated sequence of LLR metrics, of length M _x , wherein generating the second consolidated sequence of LLR metrics comprises merging the first, the second and the third sequence of LLR metrics, or merging the first consolidated sequence of LLR metrics and the third sequence of LLR metrics and generating, by the receiver, a third reconstructed first bit sequence of length M based on the second consolidated sequence of LLR metrics.

In an eighth possible implementation of the method of the seventh implementations, one or more bits from the first bit sequence are included in only one of the second bit sequence and the third bit sequence.

In a ninth possible implementation of the of the method of the seventh or eighth implementation, the third bit sequence comprises JV ₃ information bits out of the N _t information bits of the first bit sequence and does not comprise any redundancy bits, wherein 1 < N ₃ £ N _1.

In an tenth possible implementation of the of the method of any of the seventh eighth or ninth implementations, determining that the reconstructed second bit sequence is invalid comprises or consists in determining that a syndrome of the reconstructed second bit sequence is a fault syndrome.

In an eleventh possible implementation of the of the method of any of the seventh eighth or ninth implementations, the first bit sequence is a codeword of a Forward Error Correction, FEC, code, and wherein determining that the reconstructed second bit sequence is invalid comprises or consists in determining that the reconstructed second bit sequence is not a valid codeword of the FEC code.

In a twelfth possible implementation of the method of the first aspect, a method of sending a plurality of pieces of information from a transmitter to a receiver, comprising: sending each of the pieces of information from the transmitter to the receiver by executing an instance of the method of any one of preceding possible implementations of the method of the first aspect, wherein for each piece of information the JV ₂ bits of the second bit sequence are selected from the first bit sequence in accordance with a bit selection pattern applied to the first bit sequence, wherein the bit selection pattern is the same for each of the pieces of information.

In a second aspect, the disclosure relates to a method of sending information from a transmitter to a receiver, comprising operating the transmitter to: send a first signal to the receiver, the first signal carrying a first sequence of symbols, the first sequence of symbols representing a first bit sequence of length M _x , the first bit sequence comprising N ₁ information bits and (M ₁ — L^) redundancy bits, wherein 1 < /V _x < M _x ; receive a request from the receiver; and send a second signal to the receiver in response to the received request, the second signal carrying a second sequence of symbols, the second sequence of symbols representing a second bit sequence of length iV ₂ , the second bit sequence comprising N ₂ information bits out of the N ₁ information bits of the first bit sequence and not comprising any redundancy bits, wherein 1 < JV ₂ < N _.

In a third aspect, the disclosure relates to a method of receiving information from a transmitter at a receiver, the method comprising operating the receiver to: receive a first signal from the transmitter, the first signal carrying a first sequence of symbols, the first sequence of symbols representing a first bit sequence of length M _x , the first bit sequence comprising N ₁ information bits and (M ₁ — L^) redundancy bits; generate a reconstructed first sequence of symbols by demodulating the received first signal; generate a first sequence of Log Likelihood Ratio, LLR, metrics, of length M _x , by generating for each symbol of the reconstructed second sequence of symbols one or more Log Likelihood Ratio, LLR, metrics; generate a reconstructed first bit sequence of length M based on the first sequence of LLR metrics; determine that the reconstructed first bit sequence is invalid; send a request to the transmitter; receive a second signal from the transmitter, the second signal carrying a second sequence of symbols, the second sequence of symbols representing a second bit sequence of length N ₂ , the second bit sequence comprising N ₂ information bits out of the N ₁ information bits of the first bit sequence and not comprising any redundancy bits, wherein 1 < JV ₂ < N^, generate a reconstructed second sequence of symbols by demodulating the received second signal; generate a second sequence of LLR metrics, of length N ₂ , by generating for each symbol of the reconstructed second sequence of symbols one or more LLR metrics; generate a consolidated sequence of LLR metrics, of length M _x , wherein generating the consolidated sequence of LLR metrics comprises merging the first sequence of LLR metrics and the second sequence of LLR metrics; and generate a second reconstructed first bit sequence of length M based on the consolidated sequence of LLR metrics.

In a fourth aspect, the disclosure relates to a transmitter configured to: send a first signal to a receiver, the first signal carrying a first sequence of symbols, the first sequence of symbols representing a first bit sequence of length M _x , the first bit sequence comprising N information bits and (M ₁ — L^) redundancy bits, wherein 1 < /V _x < M _x ; receive a request from the receiver; and send a second signal in response to the received request, the second signal carrying a second sequence of symbols, the second sequence of symbols representing a second bit sequence of length N ₂ , the second bit sequence comprising N ₂ information bits out of the N _± information bits of the first bit sequence and not comprising any redundancy bits, wherein 1 < JV ₂ < N _.

In a fifth aspect, the disclosure relates to a receiver configured to: receive a first signal from a transmitter, the first signal carrying a first sequence of symbols, the first sequence of symbols representing a first bit sequence of length M _x , the first bit sequence comprising N ₁ information bits and (M ₁ — L^) redundancy bits; generate a reconstructed first sequence of symbols by demodulating the received first signal; generate a first sequence of Log Likelihood Ratio, LLR, metrics by generating for each symbol of the reconstructed second sequence of symbols one or more Log Likelihood Ratio, LLR, metrics; generate a reconstructed first bit sequence of length M based on the first sequence of LLR metrics; if the reconstructed first bit sequence is invalid, send a request to the transmitter; receive a second signal from the transmitter, the second signal carrying a second sequence of symbols, the second sequence of symbols representing a second bit sequence of length N ₂ , the second bit sequence comprising N ₂ information bits out of the N ₁ information bits of the first bit sequence and not comprising any redundancy bits, wherein 1 < JV ₂ < N^, generate a reconstructed second sequence of symbols by demodulating the received second signal; generate a second sequence of LLR metrics, of length N ₂ , by generating for each symbol of the reconstructed second sequence of symbols one or more Log Likelihood Ratio, LLR, metrics; generate a consolidated sequence of LLR metrics, of length M _x , wherein generating the consolidated sequence of LLR metrics comprises merging the first sequence of LLR metrics and the second sequence of LLR metrics; and generate a second reconstructed first bit sequence of length M based on the consolidated sequence of LLR metrics. Unless otherwise defined, all technical and/or scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the disclosure pertains. Although methods and materials similar or equivalent to those described herein can be used in the practice or testing of embodiments of the disclosure, exemplary methods and/or materials are described below. In case of conflict, the patent specification, including definitions, will control. In addition, the materials, methods, and examples are illustrative only and are not intended to be necessarily limiting.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

Some embodiments of the disclosure are herein described, by way of example only, with reference to the accompanying drawings. With specific reference now to the drawings in detail, it is stressed that the particulars shown are by way of example and for purposes of illustrative discussion of embodiments of the disclosure. In this regard, the description taken with the drawings makes apparent to those skilled in the art how embodiments of the disclosure may be practiced.

In the drawings:

- FIG. 1 schematically shows a system according to some embodiments of the present disclosure;

- FIG. 2 schematically shows an example of a stream of bit sequences of FEC codewords transmitted by a transmitter, according to some embodiments of the present disclosure;

- FIG. 3 schematically shows a method for retransmission of information bits only, according to some embodiments of the disclosure;

- FIG. 4 schematically shows an example of a retransmission of less information bits in the second signal from the information bits in the first signal, when the bit sequences is a FEC codeword, according to some embodiments of the disclosure;

- FIG. 5 schematically shows a comparison of Packet Error Rate (PER) dependence on Signal to Noise Ratio (SNR) for different HARQ schemes, including a scheme of retransmission of information bits only, according to some embodiments of the disclosure; and

- FIGS. 6A-6B schematically show a comparison of throughput for different HARQ schemes including a scheme of retransmission of information bits only, according to some embodiments of the disclosure. DETAILED DESCRIPTION OF EMBODIMENTS OF THE DISCLOSURE

The present disclosure, in some embodiments thereof, relates to a system and method for retransmission of incorrectly received data. More specifically, but not exclusively, the present disclosure relates to systems and methods for retransmission of incorrectly received data, where only the information bits of the data which was not received correctly are retransmitted. The incorrectly received data may be referred to herein as “incorrect data”, for short.

In a communication system, a transmitter (Tx), which is an apparatus for sending a signal, sends a signal carrying data to a receiver (Rx), which is an apparatus for receiving a signal. The signal includes a sequence of modulated symbols. The symbols represent a stream of bits which includes a pair of sequences, namely a sequence of information bits and a sequence of redundancy bits (redundancy bits are also referred to as parity bits), or a plurality of such pairs of sequences. When the signal is received at the receiver, the signal is demodulated to reconstruct the sequence of symbols. The sequence of reconstructed symbols is de-mapped into LLR metrics also known as soft bits, or LLRs for short) which are then decoded to detect the data that was sent by the transmitter. Once the signal is correctly decoded, the receiver may send according to some embodiments of the present disclosure an Acknowledgement (ACK) message to the transmitter, indicating that the data was correctly received. Sometimes the data fails to be correctly decoded and then, the receiver sends a None-Acknowledgement (NACK) message to the transmitter indicating the data was not correctly received. The NACK message is in fact a request to retransmit the incorrectly received data, and is referred to hereinafter as a ReTX-request, for short. The transmitter, in response to the ReTX-request, retransmits a signal carrying the incorrectly received data to the receiver. Within the ARQ method, the receiver discards the incorrectly received signal and the processing byproducts of the incorrectly received signal, and once the transmitter retransmits the data again, a new detection process is carried out. In the HARQ method, on the other hand, soft combining of Log Likelihood Ratio (LLR) metrics (or combining of equalized symbols) from different retransmitted/transmitted signals carrying possibly different versions of the same data is performed by the receiver. This means that the LLR metrics respective to the previously incorrectly received signal(s) are stored in a memory of the receiver and are combined with LLR metrics extracted from retransmitted signals carrying the same information, thus increasing the probability for correct data reception (after retransmission). However, usually, the retransmitted signal is constructed in one of two known methods; the first is called Chase Combining (CC), where the same signal as the original signal is retransmitted, either using the same modulation symbols or the same bit-stream as a whole, including the same sequence of information bits and the same sequence of redundancy bit as in the first transmitted signal; the second method is called Incremental Redundancy (IR), where the sequence of retransmitted redundancy bits is different than the sequence of redundancy bits carried by the first transmitted signal. There is a need to provide a method and system for retransmitting only information bits. According to some embodiments of the present disclosure, a system and method are provided for retransmitting only the sequence of information bits or a subset of the sequence of information bits without retransmitting any redundancy bits, thereby, improving the efficiency and throughput of the system and possibly also the simplicity of the design of the system.

Computer readable program instructions for carrying out operations of the present disclosure may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state setting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) may execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present disclosure.

Aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer readable program instructions.

These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including instructions which implement aspects of the function/act specified in the flowchart and/or block diagram block or blocks.

The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions/acts specified in the flowchart and/or block diagram block or blocks.

The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions. Reference is now made to FIG. 1, which schematically shows a system according to some embodiments of the present disclosure. System 100 includes a transmitter 101 and a receiver 102. The transmitter 101 has a memory 111 and a processor 112. The receiver 102 has a memory 113 and a processor 114. The transmitter 101 may comprise processing circuitry configured to perform or cause the transmitter-side operations described in this application. The processing circuitry may comprise hardware and software. The hardware may comprise analog circuitry or digital circuitry, or both analog and digital circuitry. The analog circuitry may comprise radio frequency (RF) signal generation and processing means such as a voltage- controlled oscillator, an amplifier and a mixer. The digital circuitry may comprise components such as application-specific integrated circuits (ASICs), field-programmable arrays (FPGAs), digital signal processors (DSPs), or general-purpose processors. In some embodiment, the processing circuitry comprises one or more processors and a non-transitory memory connected to the one or more processors. The non-transitory memory may carry executable program code which, when executed by the one or more processors, causes the transmitter 101 to perform the operations or methods described herein. The receiver 102 may comprise processing circuitry configured to perform or cause the transmitter-sider operations described in this application. The processing circuitry may comprise hardware and software. The hardware may comprise analog circuitry or digital circuitry, or both analog and digital circuitry. The analog circuitry may comprise radio frequency (RF) signal generation and processing means such as a voltage- controlled oscillator, an amplifier and a mixer. The digital circuitry may comprise components such as application-specific integrated circuits (ASICs), field-programmable arrays (FPGAs), digital signal processors (DSPs), or general-purpose processors. In one embodiment, the processing circuitry comprises one or more processors and a non-transitory memory connected to the one or more processors. The non-transitory memory may carry executable program code which, when executed by the one or more processors, causes the receiver 102 to perform the operations or methods described herein.

Transmitter 101 sends a first signal carrying a first sequence of symbols. The first sequence of symbols represents, for instance via Quadrature Amplitude Modulation (QAM), a first bit sequence of length M _1. The bit sequence consists of a sequence of information bits of length /Vi and a dependent sequence of redundancy bits of length R _l = M _l — where 1 <N ₁ <M ₁ ; here the N ₁ information bits represent a piece of information and are treated as a whole single unit of data which needs to be transferred to the receiver, and the R± redundancy bits accompanying the N ₁ information bits are generated from the N ₁ information bits according to a predefined encoding scheme , which is also known to the receiver 102. The receiver 102, receives the first signal and demodulates the received first signal in an attempt to reconstruct the first sequence of symbols. Then, the processor 113 of the receiver generates a first sequence of Log Likelihood Ratio (LLR) metrics of length M _x , associated with the M bits of the first bit sequence, by generating for each reconstructed symbol one or more LLR metrics. The LLR metrics are stored at the memory 114 of the receiver. Then, at the receiver, the processor 113, generates a reconstructed first bit sequence of length M based on the sequence of the LLR metrics. In case the receiver 102 determines the reconstructed first bit sequence is invalid, meaning that the reconstructed first bit sequence was incorrectly received, the receiver 102, sends a ReTX-request message (NACK) to the transmitter 101. The transmitter 101, receives the ReTX-request and in response, according to some embodiments of the present disclosure, sends a second signal carrying a second sequence of symbols, which represents a sequence of only N ₂ information bits out of the sequence information bits, where 1<JV ₂ <N ₁ , namely without any bits out of the sequence of the R± redundancy bits. This way the efficiency of the system increases.

According to some embodiments of the present disclosure, the transmitter 101 sends the second signal so that it carries all the information bits of the first bit sequence and then N ₂ =N _1. According to some other embodiments of the present disclosure, the transmitter 101 sends the second signal so that it carries less than all of the information bits of the first bit sequence, namely such that 1 < iV ₂ <lV _:L . The retransmitted sequence of information bits thus comprises JV ₂ bits, where JV ₂ is equal or smaller than N _±. The receiver 102 receives the second signal and generates a reconstructed second sequence of symbols by demodulating the received second signal. Processor 114 of the receiver generates a second sequence of LLR metrics of length N ₂ by generating for each symbol of the reconstructed second sequence of symbols one or more LLR metrics. Then, the receiver 102 generates a consolidated sequence of M LLR metrics, which includes a merging of the first sequence of M LLR metrics and the second sequence of JV ₂ LLR metrics. This means, that the receiver merges the sequence of LLR metrics generated from the first signal and the LLR sequence generated from the second signal to one consolidated sequence of LLR metrics. Finally, the receiver 102 generates a reconstructed bit sequence of length M based on the consolidated sequence of M LLR metrics.

According to some embodiments of the present disclosure, merging the sequences of LLR metrics to the consolidated sequence of LLR metrics is done by adding to each of JV ₂ metrics from the M ₁ metrics of the first sequence of LLR metrics a value of one of the JV ₂ metrics of the second sequence of LLR metrics.

According to some embodiments of the present disclosure, the receiver determines whether the reconstructed first bit sequence is valid or not by encoding (or re-encoding) the N _± information bits out of the reconstructed first bit sequence, using the same encoding scheme as used by the transmitter when the transmitter generated the R _± redundancy bits of the first bit sequence, and comparing the resulting R ₁ extra bits to the respective R _± bits of the reconstructed first bit sequence; an exact match between these two bit sequences of length R ₁ implies that the reconstructed first bit sequence is valid and leads to the receiver deciding that the piece of information comprising the N _± information bits was received correctly, whereas any discrepancy between the two sequences implies an invalid reconstructed first bit sequence and thus incorrect decoding of the piece of information.

According to some embodiments the decision whether the reconstructed first bit sequence is valid or not can be done efficiently via a method called Syndrome Check, using a parity check matrix: if the result of multiplication of the reconstructed first bit sequence (viewed as a vector over the binary number field) by the parity check matrix yields zero, then the receiver determines that the reconstructed first bit sequence is valid; otherwise, if the result of the multiplication is nonzero (i.e., resulting in a so-called “fault syndrome”), then the reconstructed first bit sequence is deemed invalid by the receiver.

According to some embodiments of the present disclosure, the transmitter transmits a codeword of a Forward Error Correction (FEC) code as the bit sequence. The FEC code may be a Low-Density Parity Check (LDPC) code, for example. In some embodiments of the present disclosure, the receiver determines that the reconstructed first bit sequence is invalid when the reconstructed first bit sequence is not a valid codeword of the FEC code. In case the transmitter transmits a codeword of a FEC code and the receiver determines the received codeword is invalid, the receiver sends a ReTX-request to the transmitter and the transmitter sends in response only the information bits of the indicated invalid codeword, without the redundancy bits.

FIG. 2 schematically shows an example of a signal containing a stream of FEC codewords transmitted by a transmitter. In stream 201, codewords # 1 -# 11 are transmitted from the transmitter to the receiver. Each codeword includes a sequence of information bits and a sequence of redundancy (parity) bits. Codeword #3 includes a sequence of information bits 210, where N ₁ = 911 and an accompanying sequence of parity bits 211, where R ₁ = M ₁ — N ₁ = 911, so that the FEC code rate is = 1/2 in this example. Similarly, codeword #5 includes a sequence of information bits 212, where N ₁ = 911 and an accompanying sequence of parity bits 213, where R ₁ = M ₁ — N ₁ = 911. In this example, codewords #3 and #5 are incorrectly received, which means the receiver determined that codewords #3 and #5 are invalid upon reception of the transmission from the transmitter. The receiver sends a NACK message to the transmitter, with a request to retransmit codewords #3 and #5, which were not received correctly. The transmitter, in response, according to some embodiments of the present disclosure, retransmits the bit stream 202 comprising the sequence of information bits 210 of codewords #3, where JV ₂ = 911 and the sequence of information bits 212 of codeword #5, where JV ₂ =911, without the sequences of redundancy bits 211 and 213, respectively.

Reference is now made to FIG. 3, which schematically shows a flow chart representing a method for retransmitting only the information bits of an incorrectly received data, according to some embodiments of the present disclosure. At 301 a first signal carrying a first sequence of symbols, is transmitted by the transmitter to the receiver. The first sequence of symbols represents a first bit sequence of length M ₁ . The first bit sequence includes N ₁ information bits and (M _l — redundancy bits, where 1 <N ₁ <M ₁ . The N ₁ information bits represent a piece of information. At 302, the first signal is received by the receiver and a reconstructed first sequence of symbols is generated by demodulating the received first signal. At 303 a first sequence of Log Likelihood Ratio (LLR) metrics, of length M _x , is generated by the processor of the receiver, by generating for each symbol of the reconstructed first sequence of symbols one or more LLR metrics. At 304 a reconstructed first bit sequence of length M is generated by the processor of the receiver, based on the first sequence of LLR metrics. At 305, it is determined by the receiver, that the reconstructed first bit sequence is invalid (i.e. the reconstructed first bit sequence was incorrectly received or incorrectly decoded). Then at 306, a ReTX-request is sent to the transmitter by the receiver. At 307, the ReTX-request is received by the transmitter. In response, at 308 a second signal is sent by the transmitter to the receiver. The second signal carries a second sequence of symbols, which represents a second bit sequence, which includes JV ₂ information bits from the N _t information bits of the first bit sequence without any redundancy bits, wherein 1 <N ₂ £N ₁ . At 309, the second signal is received by the receiver and a reconstructed second sequence of symbols is generated by the receiver by demodulating the received second signal. At 310, a second sequence of LLR metrics of length N ₂ is generated by the processor of the receiver based on the reconstructed second sequence of symbols, by generating for each symbol one or more LLR metrics. At 311, a consolidated sequence of LLR metrics of length M is generated by the processor of the receiver, by merging the first sequence of LLR metrics and the second sequence of LLR metrics. Finally, at 312, a second reconstructed first bit sequence of length M is generated by the processor of the receiver based on the consolidated sequence of LLR metrics. Extracting from the second reconstructed first bit sequence the N information bits, representing a candidate for the piece of information, which the transmitter tried to transfer to the receiver, the likelihood of correctly receiving this piece of information is increased. Moreover, when taking into account the overhead incurred by the retransmission process, the efficiency and throughput of the transmission increases as fewer bits are carried by the second signal relative to prior art retransmission schemes. The retransmission of only information bits is beneficial, taking advantage of the fact that the first sequence of LLR metrics (corresponding to the first bit sequence) may be reused in combination with the (shorter) second sequence of LLR metrics (corresponding to the second bit sequence) to correctly decode the first bit sequence at higher probability.

According to some embodiments of the present disclosure, the transmitter signals to the receiver that it is retransmitting an incorrectly received bit sequence with information bits only. For example, in a Wi-Fi communication system based on a variant of a IEEE 802.11 standard, the signaling may comprise a bit in the SIG-A or SIG-B fields of the physical layer (PHY) preamble of the transmitted frame.

According to some embodiments of the present disclosure, the transmitter sends in the second signal JV ₂ information bits, which include all the N _t information bits of the first signals, so that the relation N ₂ = N ₁ holds. According to some other embodiments of the present disclosure, the transmitter sends in the second signal JV ₂ information bits, which include less than all of the /Vi information bits of the first signal, and then 1 < N ₂ < N _t . An example for sending less information bits in the second signal may be when the transmitter deploys an Orthogonal Frequency Division Multiplexing (OFDM) based modulation scheme to generate the second signal. In this case, according to some embodiments of the present disclosure, the number of information bits transmitted in the second signal is set so that after modulation, the data fully occupies an integer number of OFDM symbols. Therefore, the number of information bits retransmitted in the second signal may be smaller than the number of information bits transmitted in the first signal, in order to reduce the second signal duration and thus increase the efficiency of the retransmission scheme. According to some embodiments of the present disclosure, generating the consolidated sequence of LLR metrics is done by adding to each N ₂ metrics out of the M metrics of the first sequence of LLR metrics a value of one of the JV ₂ metrics of the second sequence of LLR metrics.

According to some other embodiments of the present disclosure, when transmitting the second signal is not enough for correctly reconstructing the first bit sequence by the receiver, the receiver sends an additional ReTX-request to the transmitter to retransmit the data carried by the first signal. The transmitter in response sends a third signal which carries a third sequence of symbols, which represents a third bit sequence of length M ₃ , which includes M ₃ bits from the first bit sequence, where 1 <M ₃ <M _1. In this case, the M ₃ bits may be the information bits and/or redundancy bits. The receiver receives the third signal and generates a reconstructed third sequence of symbols by demodulating the received third signal. The processor of the receiver then generates a third sequence of LLR metrics of length M ₃ , by generating for each symbol of the reconstructed third sequence of symbols one or more LLR metrics. The processor of the receiver then generates a second consolidated sequence of LLR metrics of length M _x , by merging the first, second and third sequences of LLR metrics, or by merging the first consolidated sequence of LLR metrics and the third sequence of LLR metrics. Finally, the processor of the receiver generates a third reconstructed first bit sequence of length M based on the second consolidated sequence of LLR metrics. According to some embodiments of the disclosure, in this case, one or more bits from the first bit sequence are included in only one of the second bit sequence and the third bit sequence.

According to some embodiments of the disclosure, the third bit sequence comprises JV ₃ information bits out of the N information bits of the first bit sequence and does not comprise any redundancy bits, where 1 < iV ₃ < N _.

According to some embodiments of the disclosure, in case the third reconstructed first bit sequence is determined to be invalid by the receiver, the process described above of reconstructing a third consolidated first bit sequence is repeated again. The process repeats itself to construct a fourth consolidated first bit sequence and so on n times, where n is a predefined number, or until the reconstructed first bit sequence is determined to be valid by the receiver.

According to some embodiments of the disclosure, when the transmitter transmits the second bit sequence to the receiver, the selection of JV ₂ bits out of the N _t information bits of the first bit sequence does not depend on the piece of information. In addition, the selection of bits from the first bit sequence does not depend on which bits from the first bit sequence was not received correctly when sending the first bit sequence. This means that the second bit sequence is constructed in the same manner for each piece of information, i.e., for each instance of sending the second bit sequence. The selection of the bits from the first bit sequence is done according to a bit selection pattern which is known also to the receiver (either by being predefined or by being signaled from the transmitter to the receiver), and the same pattern is applied for each of the pieces of information sent from the transmitter to the receiver. This allows for a simple implementation of the method disclosed herein. According to some embodiments of the disclosure, the bit selection pattern used for selecting the bits to be retransmitted depends on one or both lengths M and N _t of the first bit sequence and the information bits therein, respectively, but not on the values of the bits included in the first bit sequence. According to some other embodiments of the disclosure, the bit selection pattern depends on the retransmission attempt index, namely, for instance, a different pattern may be used for constructing the third bit sequence from the first bit sequence than the pattern used for constructing the second bit sequence from the first bit sequence.

According to some embodiments of the disclosure, determining by the receiver that the reconstructed second bit sequence is invalid consists in determining that the syndrome of the reconstructed second bit sequence is a fault syndrome.

According to some embodiments of the disclosure, the first bit sequence is a codeword of a Forward Error Correction, FEC, code, and determining that the reconstructed second bit sequence is invalid consists in determining that the reconstructed second bit sequence is not a valid codeword of the FEC code.

FIG. 4 schematically shows an example of a retransmission of less information bits in the second signal than the information bits in the first signal, when the bit sequences are FEC codewords, according to some embodiments of the present disclosure. A signal 410, which contains 11 codewords, is sent from the transmitter to the receiver. Each codeword contains information bits and redundancy (parity) bits. Codeword #3 contains information bits 403 and redundancy bits 404, where the number of information bits is N = 911 and the number of redundancy bits is = M — N ₁ = 9\\. Similarly, codeword #5 contains information bits 405 and redundancy bits 406, where the number of information bits is N = 911 and the number of redundancy bits is R = M — N _± = 911. In this example codewords #3 and #5 are incorrectly received at the receiver. The receiver sends a ReTX-request for codewords #3 and #5, and the transmitter sends in response information bits 410, where N ₂ = BOO from the 911 information bits 403 of codeword #3 and information bits 412, where N ₂ = 800 from the 911 information bits 405 of codeword #5, without sending any of the redundancy bits 404 and 406. The information bits 413 where N ₂ = 800 of codeword #3 and the information bits 415 where N ₂ = 800 of codeword #5 together comprise the retransmitted bit stream 402.

According to some embodiments of the disclosure, when the second bit sequence is shorter than the first bit sequence (namely i.e., not all of the N ₁ information bits are included in the second bit sequence, then, the transmitter utilizes a dataset mapping. The dataset mapping is used for identifying, which information bits from the N ₁ information bits are transmitted in the second bit sequence as the retransmitted JV ₂ information bits.

According to some embodiments of the disclosure, the receiver utilizes a dataset mapping, which matches the dataset mapping utilized by the transmitter. The dataset mapping utilized by the receiver, identifies which N ₂ LLR metrics in the second sequence of LLR metrics are to be combined with which N ₂ LLR metrics out of the M LLR metrics in the first sequence of LLR metrics, when generating the consolidated sequence of LLR metrics. The match between the dataset mapping utilized by the receiver and the dataset mapping utilized by the transmitter is achieved by a predefined handshake procedure or signaling from the transmitter to the receiver.

According to some embodiments of the disclosure, the transmitter deploys a multi carrier modulation scheme, such as OFDM, to generate the first signal and the symbols transmitted in the first signal are interleaved according to a predefined prescription prior to being mapped onto subcarriers. According to some embodiments of the disclosure, the transmitter interleaves the symbols of the second signal according to a possibly different predefined prescription prior to being mapped onto the same or different subcarriers than the subcarriers the symbols were mapped onto during the generation of the first signal. The interleaving and subcarrier mapping prescriptions are made available to the receiver receiving the first and second signals and the processor of the receiver utilizes the prescriptions while receiving and decoding the first and second signals.

According to some embodiments of the disclosure, when the transmitter transmits in the second signal JV ₂ information bits, and N ₂ <N ₁ , (i.e. the information bits in the second signal are fewer than the information bits in the first signal), the number N ₂ of information bits transmitted is agreed upon by the transmitter and by the receiver through a predefined handshake procedure or signaling from the transmitter to the receiver.

Reference is now made to FIG. 5, which shows a schematic comparison of Packet Error Rate (PER) dependence on Signal to Noise Ratio (SNR). These are evaluation results obtained in simulations of a standard IEEE 802.1 lax communication link, but using different retransmission schemes, for each of several Modulation and Coding Schemes (MCSs). The scenario considered is of a 2x2 Multi-Input Multi-Output (MIMO) antenna configuration, with a TGn-D Non Line Of Sight (NLOS) channel model in 20MHz channel bandwidth, using perfect channel estimation and Minimum Mean Square Error (MMSE) demodulator at the receiver. The retransmission schemes considered are:

• No HARQ;

• HARQ with Chase combining (entire codeword is retransmitted upon failure); and

• HARQ with retransmission of information bits only, where only information bits are retransmitted upon decoding failure at the receiver, according to some embodiments of the present disclosure.

It can be seen that the retransmission scheme of the information bits only provides better results (lower PER for a given SNR) than the “No HARQ” scheme. The Chase Combining scheme, where the whole codeword is retransmitted, exhibits the best PER performance out of the three compared schemes, yet at the higher overhead, whose impact is taken into account next in FIGs. 6A-6B, in the discussion of the throughput.

FIGs. 6A-6B show simulation results of a comparison of the link throughput in the same scenario considered in FIG. 5 - taking into account all overheads (Preamble, Short Interframe Space (SIFS), ACK message durations, and the like) - where two MCS selection schemes are deployed. In FIG. 6 A an optimal MCS selection is deployed - choosing for any given SNR the MCS, which yields the highest throughput. FIG. 6B presents the results when a sub-optimal (emulating a practical) MCS selection is deployed - for No-HARQ, choosing for any given SNR the MCS which yields the highest throughput but only as long as PER<10% for first transmission; and for the two HARQ schemes, choosing the MCS which yields the highest throughput but only as long as PER<20% for first transmission.

In both cases, of the optimal and sub-optimal MCS selection strategies, codeword retransmission with information bits only, according to some embodiments of the disclosure, yields superior performance and it can be seen that codeword retransmission with information bits only is the best retransmission scheme in all cases. The descriptions of the various embodiments of the present disclosure have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

It is expected that during the life of a patent maturing from this application many relevant models for retransmission of information bits only will be developed and the scope of the term model for retransmission of information bits only is intended to include all such new technologies a priori.

As used herein the t “about” refers to ± 10 %.

The terms "comprises", "comprising", "includes", "including", “having” and their conjugates mean "including but not limited to". This term encompasses the terms "consisting of' and "consisting essentially of'.

The phrase "consisting essentially of' means that the composition or method may include additional ingredients and/or steps, but only if the additional ingredients and/or steps do not materially alter the basic and novel characteristics of the claimed composition or method.

As used herein, the singular form "a", "an" and "the" include plural references unless the context clearly dictates otherwise. For example, the term "a compound" or "at least one compound" may include a plurality of compounds, including mixtures thereof.

The word “exemplary” is used herein to mean “serving as an example, instance or illustration”. Any embodiment described as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments and/or to exclude the incorporation of features from other embodiments.

The word “optionally” is used herein to mean “is provided in some embodiments and not provided in other embodiments”. Any particular embodiment of the disclosure may include a plurality of “optional” features unless such features conflict.

Throughout this application, various embodiments of this disclosure may be presented in a range format. It should be understood that the description in range format is merely for convenience and brevity and should not be construed as an inflexible limitation on the scope of the disclosure. Accordingly, the description of a range should be considered to have specifically disclosed all the possible subranges as well as individual numerical values within that range. For example, description of a range such as from 1 to 6 should be considered to have specifically disclosed subranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6 etc., as well as individual numbers within that range, for example, 1, 2, 3, 4, 5, and 6. This applies regardless of the breadth of the range.

Whenever a numerical range is indicated herein, it is meant to include any cited numeral (fractional or integral) within the indicated range. The phrases “ranging/ranges between” a first indicate number and a second indicate number and “ranging/ranges from” a first indicate number “to” a second indicate number are used herein interchangeably and are meant to include the first and second indicated numbers and all the fractional and integral numerals therebetween.

It is appreciated that certain features of the disclosure, which are, for clarity, described in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features of the disclosure, which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable subcombination or as suitable in any other described embodiment of the disclosure. Certain features described in the context of various embodiments are not to be considered essential features of those embodiments, unless the embodiment is inoperative without those elements.

Although the disclosure has been described in conjunction with specific embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, it is intended to embrace all such alternatives, modifications and variations that fall within the spirit and broad scope of the appended claims.

All publications, patents and patent applications mentioned in this specification are herein incorporated in their entirety by reference into the specification, to the same extent as if each individual publication, patent or patent application was specifically and individually indicated to be incorporated herein by reference. In addition, citation or identification of any reference in this application shall not be construed as an admission that such reference is available as prior art to the present disclosure. To the extent that section headings are used, they should not be construed as necessarily limiting. In addition, any priority document(s) of this application is/are hereby incorporated herein by reference in its/their entirety.