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Patent Searching and Data


Title:
SYSTEMS AND/OR METHODS FOR ANOMALY DETECTION AND CHARACTERIZATION IN INTEGRATED CIRCUITS
Document Type and Number:
WIPO Patent Application WO/2021/002914
Kind Code:
A3
Abstract:
Systems, methods, and computer readable medium described herein relate to techniques for characterizing and/or anomaly detection in integrated circuits such as, but not limited to, field programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs). In one example aspect of certain example embodiments, a fully digital technique relies on the pulse width of signals propagated through a path under test. In another example aspect, the re-configurability of the integrated circuit is leveraged to combine the pulse propagation technique with a delay characterization technique to yield better detection of certain type of Trojans and the like. Another example aspect provides for running the test through reconfigurable path segments in order to isolate and identify anomalous circuit elements. Yet another example aspect provides for performing the characterization and anomaly detection without requiring golden references and the like.

Inventors:
DICKENS JASON (US)
Application Number:
PCT/US2020/027433
Publication Date:
February 11, 2021
Filing Date:
April 09, 2020
Export Citation:
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Assignee:
GRAMMATECH INC (US)
International Classes:
G01R31/3183; G01R31/3177; G01R31/3185; G01R31/319
Foreign References:
US20090271134A12009-10-29
US20140347088A12014-11-27
US4829521A1989-05-09
US5436853A1995-07-25
US20200326373A12020-10-15
Other References:
CHEN: "A New Path Delay Test Scheme Based on Path Delay Inertia", PROCEEDINGS OF THE 13TH ASIAN TEST SYMPOSIUM (ATS 2004, 15 November 2004 (2004-11-15), pages 140 - 144, XP010757159, DOI: 10.1109/ATS.2004.11
Attorney, Agent or Firm:
ROBERTS, Jonathan, A. (US)
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