Cross-Reference to Related Applications

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 60/633,747, filed December 7, 2004, which is hereby incorporated herein by reference in its entirety.

Background of the Invention

[0002] The present invention relates to continuous-time signals. More particularly, this invention relates to the modulation of continuous-time signals.

[0003] Modulation is the process of adding information to a carrier signal, so that the information signal can be transmitted at a given frequency. Generally, the amplitude, frequency, and phase of a carrier signal can be modulated to place information on the carrier signal. In some cases, when a digital radio-frequency (RF) modulator is used to modulate a carrier signal, an analog-to-digital conversion (ADC) of an analog signal to be modulated needs to be performed. This ADC typically requires a clock for sampling the input analog signal. U.S. Patents Nos. 4,403,197 and 4,580,111 describe modulation techniques that are performed in discrete-time using a clock for sampling an input analog signal. However, such sampling may result in aliasing of the signal and quantization error in the base band. It would therefore be desirable to minimize the effects of aliasing and quantization error in the base band signal.

Summary of the Invention

[0004] Methods and systems for modulating a continuous-time signal are presented. More particularly, the present invention provides techniques and systems for converting an analog signal to a continuous-time digital signal, and using this signal to modulate a radio frequency signal, in continuous-time. This may be accomplished through the use of a continuous-time analog-to-digital converter. When modulating the radio frequency signal with the continuous-time digital signal, various kinds of modulation may be utilized such as

amplitude, frequency, phase, and/or any combination of the three. In some embodiments, a digital signal processor may be added to the system to process the continuous-time digital signal.

[0005] In accordance with the present invention, certain embodiments feature a continuous-time analog-to-digital converter that simultaneously produces two or more continuous-time digital signals, and a digital input signal modulator coupled to the continuous-time analog-to-digital converter that produces a modulated output in response to the two or more continuous-time digital signals.

[0006] Further in accordance with the present invention, certain embodiments feature a method for comparing in continuous-time the input signal to two or more thresholds, producing simultaneously two or more intermediate signals based on the two or more thresholds, encoding the two or more intermediate signals into a continuous-time digital output, and producing a modulated signal based on the values of the continuous-time digital output.

[0007] Still further in accordance with the present invention, certain embodiments feature a technique for simultaneously producing two or more continuous-time digital signals in response to the input signal, and a technique for receiving and modulating the two or more of continuous-time digital signals and producing a modulated output.

Brief Description of the Drawings

[0008] The above and other advantages of the present invention will be apparent upon consideration of the following detailed description, taken in conjunction with accompanying drawings, in which like reference characters refer to like parts throughout, and in which:

[0009] FIG. 1 is a graph representing a continuous-time Analog-to-Digital conversion (ADC) in accordance with certain embodiments of the present invention;

[0010] FIG. 2 is a block diagram representing an un-clocked ADC modulation system in accordance with certain embodiments of the present invention;

[0011] FIG. 3 is a block diagram representing a detailed view of the un-clocked ADC system in accordance with certain embodiments of the present invention;

[0012] FIG. 4 is a block diagram representing a detailed view of a modulator in accordance with certain embodiments of the present invention;

[0013] FIG. 5 is a block diagram representing an un-clocked ADC modulation system with digital signal processing in accordance with certain embodiments of the present invention; and

[0014] FIG. 6 is a block diagram representing a detailed view of a digital signal processor in accordance with certain embodiments of the present invention.

Detailed Description of the Invention

[0015] As stated above, the present invention relates to the modulation of continuous- time signals. More particularly, this invention relates to techniques and systems for converting an analog signal to a digital signal and modulating the digital signal in continuous- time. Continuous-time digital modulation may be accomplished in accordance with the present invention by digitizing the analog input signal without sampling in time (i.e., without using a clock to digitize the analog input signal). By implementing a digitizing technique without using sampling, aliasing of the signal can be avoided and introduction of quantization error into the base band may be reduced.

[0016] In certain embodiments of the present invention, a set of data points (t;, xø may be used to describe a continuous-time digital signal, where x; represents an absolute amplitude value, and t; represents the time when the amplitude value was met or passed. In some embodiments of the present invention, it may be desirable to represent changes in amplitude (i.e., relative amplitude values) rather than absolute amplitude values so that a type of delta modulation signal may be implemented.

[0017] The quantized and digitized information related to an input analog signal (e.g., the set of data points) may be stored in a memory medium (such as a magnetic medium, optical medium, or any other suitable storage medium) for later transmission and/or processing.

[0018] FIG. 1 illustrates a graph 100 showing the quantization and digitization of an analog signal x(t) 104 into a quantized continuous-time signal w(t) 106 in accordance with certain embodiments of the present invention. As shown, graph 100 contains level lines w,- 102, input signal x(t) 104, quantized signal w(t) 106, and time points U 108. Level lines w,-

102 represent amplitude values that mark thresholds for quantized signal w(t) 106. Quantized signal w(t) 106 results when input signal x(t) 104 is approximated to level lines w _t 102. As illustrated, input signal x(t) 104 is approximated to the next higher level line when input signal 104 x(t) is more than halfway between two level lines w,- 102. Likewise, if the input signal falls below the halfway point between level lines W ₁ - 102, then quantized signal w(t) 106 drops to the lower level line. Other suitable transition points may additionally and/or alternatively be used.

[0019] As illustrated in FIG. 1, digital bits 110, 112, and 114 correspond to level lines w, 102 and the time periods U 108. Each level line corresponds to a bit pattern comprising bit b _k (t) 110, bit b _k ](t) 112, bit bk^t) 114 and so on, where bit bk(t) 110 is the least significant bit and bit bk^t) 114, for example, is the most significant bit. As can be seen, the transitions between the bit patterns may occur at any time rather than at predetermined instants of time. The ability to transition at any point in time, rather than at specified time points, makes the digital representation a continuous-time digital representation of input signal x(t) 104. Although three bits are shown in the continuous-time signal, it should be understood that the quantized signal w(t) 106 may include any number of bits. Other embodiments for representing an input analog signal with a quantized and digitized continuous-time signal may also be used.

[0020] As shown in FIG. 2, a block diagram of a continuous-time digital modulator system 200 is illustrated in accordance with certain embodiments of the present invention. System 200 includes an analog input 202, a continuous-time Analog-to-Digital (AJO) converter 204, a continuous-time digital signal 206, a digital modulator 208, and a modulated output 210. In system 200, analog input 202 is converted into digital signal 206 by continuous-time A/D converter 204 as described above in connection with FIG. 1. Modulator 208 uses the continuous-time digital signal 206 to modulate a radio frequency signal 212 from RF source 214, in order to form modulated output 210.

[0021] FIG. 3 illustrates an embodiment of A/D converter 204 in more detail. As shown, A/D converter 204 may include an analog input 202, level detectors 302, level outputs 304, an output logic device 306, and a continuous-time digital signal 206. As shown, a plurality of level detectors 302 compare input signal 202 to quantization level thresholds provided by reference voltages VREF.I, VREF,2 ₅ VREF,3 _> and VREF,4- A level detector may be implemented using an operational amplifier as a comparator or with any other suitable device. Level

outputs 304 encode the level values from level detectors 302. Output logic device 306 converts level outputs 304 into a binary digital signal 206. Output logic device 306 may be implemented by using a look-up table or other suitable logic.

[0022] FIG. 4 illustrates in more detail a modulator 208 in accordance with certain embodiments of the present invention. Modulator 208 includes a continuous-time digital signal 206, a radio frequency (RF) source 402, a plurality of power amplifiers 404 and 406, a plurality of transformers 408 and 410, a load 420, and modulated output 210. In modulator 208, power amplifiers 404 and 406 are used to modulate RF source 214 according to continuous-time digital signal 206. The modulation may occur by using the binary continuous-time digital signal 206 to turn on and turn off power amplifiers 404 and 406. The modulation may be amplitude modulation with the switching of power amplifiers 404 and 406 changing the amplitude of the modulated signal that is outputted by modulator 208.

[0023] Each power amplifier may be identical to other power amplifiers or different from them. For example, power amplifiers 404 and 406 may be equally weighted, binary weighted, or a mixture of the two. The power amplifiers may be implemented using any suitable technologies, such as metal-oxide-semiconductor field effect transistors (MOSFET), insulated gate bipolar transistors (IGBT), bipolar junction transistors (BJT), MOS-controlled thyristors (MCT), gate-turn-off thyristors (GTO), and/or any other suitable technologies.

[0024] As shown, modulated output 210 is fed to load 420, which can be an antenna, through transformers 408 and 410. Each of transformers 408 and 410 may include a corresponding primary 412 or 414 and a corresponding secondary 416 or 418. The secondaries 418 and 416 may each act as an independent signal source so that the signals provided by the transformers can additively combine with one another to form modulated output 210. Although only two amplifiers 404 and 406 and two transformers 408 and 410 are shown in FIG. 4, and suitable number of these devices may be used.

[0025] In some embodiments, an RF phase shifter may be placed before one or more of power amplifiers 404 and 406 to selectively adjust the phase of the signals inputted to amplifiers 404 and 406 from RF source 402. The phase changes of the RF phase shifters can be digitally controlled and may be controlled by continuous-time digital signal 206.

[0026] Similarly, in certain embodiments, the frequency of the RF source may be adjusted by digital signal 206 to permit modulation of the frequency of the RF source signal. In some embodiments, multiple aspects of the RF source are adjusted, such as the frequency, phase, and amplitude of the signal. Also varying schemes of modulation such as amplitude- shift keying, phase-shift keying, frequency-shift keying, amplitude modulation, frequency modulation, or any applicable combination may be used for modulating and transmitting a signal.

[0027] FIG. 5 illustrates a signal modulation system 500 with a continuous-time digital signal processor (DSP) 506 before a modulator 508 in accordance with certain embodiments of the present invention. The addition of continuous-time DSP 506 may allow manipulation and adjustment of the signal before modulation. Digital signal processing can be used to change the characteristics of the signal. For example, digital signal processing may be used to implement digital filters such as a low-pass filter, a high-pass filter, a notch filter, a comb filter, a smoothing filter, or any other desirable filter. After the digital processing is complete, modulator 508 receives the output of continuous-time DSP 506 and can use the digital signal, as described above, to modulate the digital signal onto a carrier frequency and output a processed modulated signal 510.

[0028] FIG. 6 illustrates a more detailed view of a continuous-time DSP 506 in accordance with certain embodiments of the present invention. Continuous-time DSP 506 includes a continuous-time DSP input 602, a continuous-time delay 604, a delayed signal 606, a coefficient multiplier 608, a delayed multiplied signal 610, and a binary-weighted adder 612. Binary-weighted adder 612 may be optionally replaced with a non-binary- weighted adder depending on whether output logic device 306 is used to encode the level value signals as binary digital signals.

[0029] As shown, continuous-time delay 604 receives continuous-time DSP input 602 and outputs delayed signal 606 along with the original continuous-time DSP input 602 to the coefficient multiplier 608. In some embodiments, continuous-time delay 604 may include one set of output signals corresponding to delayed signal 606. Delayed signal 606 and continuous-time DSP input 602 may be multiplied with varying coefficients in coefficient multiplier 608. The coefficients may correspond to a transfer function and may be set to implement functions, such as a low-pass filter. Delayed multiplied signal 610 from coefficient multiplier 608 may then be inputted into binary-weighted adder 612, which may

perform a weighted summation with respect to the relative significance of the bits within delayed multiplied signal 610 obtained from the A/D conversion.

[0030] In continuous-time delay 604, each bit of continuous-time DSP input 602 may be delayed by a time period T. In some embodiments, continuous-time delay 604 comprises a cascade of logic inverters, with one or more coupled with load capacitances matched to the inverter's current drive capability to produce a specified switching time. The delay provided by the logic inverters can be set to a precise value by making the inverter's current drive capability adjustable and locking the inverter's responses to an external clock.

[0031] The operation of coefficient multiplier 608 may be illustrated using an example involving a continuous-time DSP implementing an echo filter. In such an implementation, continuous-time DSP input 602 and delayed signal 606 may be passed to coefficient multiplier 608. Continuous-time DSP input 602 may then be multiplied by one or more coefficients C _A , and delayed signal 606 may be multiplied by one or more coefficients Cβ. This "multiplication" may be performed using AND gates or a suitable substitute. Coefficient C _A may include three bits, C ₁ , C ₂ and C ₃ and coefficient C _B may include three bits C ₁ , C ₂ and C ₃ . For each bit in input signal 602, coefficient multiplier 608 may produce six bits of data. For example, if the most significant bit (MSB) from continuous-time DSP input 602 is called D2, the resulting logical equation is CrD2, C ₂ -D2, C ₃ -D2, C ₁ -D ² 2, C ₂ -D ² 2 and C ₃ -D ² 2, where D2 is continuous-time DSP input 602, and D ² 2 is the delayed signal 606.

[0032] This data may then be sent to binary-weighted adder 612 which sums the resulting bits of data in one or more summing stages. The one or more summing stages may include adders, each of which adds the delayed signal 606 products to the continuous-time DSP input 602 products for a particular bit to produce an intermediate sum.

[0033] In general, the concepts this example represents can readily be extended to more delays, coefficients, and bits. In addition, although the above example is implemented using a non-recursive structure, the technique described can be extended to include filters with feedback loops. When feedback loops are present, the output of the continuous-time DSP may be processed in a manner similar to that described above and may be fed back to an internal point in the processor.

may be processed in a manner similar to that described above and may be fed back to an internal point in the processor.

[0034] As mentioned above, a continuous-time DSP may use a transfer function to modify an input signal. A general transfer function can be developed where the delays are represented by e ^~sT , in which s is the Laplace transform variable and T is the continuous-time delay between taps. Thus, in the case of integer n, where N is the number of delays in continuous-time DSP 506, each continuous-time bit may be processed by a transfer function of the form:

H(e ^sT ) = f _j c _n e- ^T (1)

[0035] Continuous-time DSP input 602 may be represented as a binary-weighted sum of individual bits, each of which is processed by transfer function (1). The binary-weighted sum formed by binary-weighted adder 612 therefore corresponds to continuous-time DSP input 602 processed by the same transfer function (1). The transfer function (1) may correspond to that of a classical analog transmission-line filter and may be identical to the corresponding transfer function H(z) of a conventional digital filter.

[0036] Substituting jω for s in transfer function (1) shows that the frequency response is periodic, with a period of 2π/T. Because the continuous-time DSP 506 does not use sampling in time, there should be no aliasing in the filtered output. For example, an input at a frequency ω may produce an output at a frequency ω, regardless of the value of ω.

[0037] Although the present invention has been described and illustrated in the foregoing exemplary embodiments, it is understood that the present disclosure has been made only by way of example, and that numerous changes in the details of implementation of the invention may be made without departing from the spirit and scope of the invention, which is limited only by the claims which follow.