Title:
THIN-FILM TRANSISTOR ARRAY AND IMAGE DISPLAY DEVICE
Document Type and Number:
WIPO Patent Application WO/2014/155998
Kind Code:
A1
Abstract:
Provided are: a thin-film transistor array capable of suppressing the blocking of via holes by a protective layer material and capable of improving yield; and an image display device comprising same. The thin-film transistor array comprises at least: an insulating substrate; a gate electrode (11); a gate insulating layer; a source electrode; source wiring (13a); a drain electrode (14); a semiconductor layer (15); a protective layer (16) covering the semiconductor layer (15); an interlayer insulating film; and a pixel electrode. The protective layer (16) is stripe-shaped, parallel to the source wiring (13a). The center positions (A) of via holes (17a) in the interlayer insulating film provided for conduction between the drain electrode (14) and the pixel electrode are positioned on a straight line (C) parallel to a stripe passing through the center point between mutually adjacent stripe-shaped protective layers, or are positioned at a distance of no more than 40 µm from the straight line (C).
Inventors:
MIYAIRI YUKARI
Application Number:
PCT/JP2014/001301
Publication Date:
October 02, 2014
Filing Date:
March 07, 2014
Export Citation:
Assignee:
TOPPAN PRINTING CO LTD (JP)
International Classes:
G09F9/30; H01L21/336; H01L29/786
Domestic Patent References:
| WO2011122205A1 | 2011-10-06 |
Foreign References:
| JP2002151522A | 2002-05-24 | |||
| JP2002268084A | 2002-09-18 | |||
| JP2010181785A | 2010-08-19 | |||
| JP2008270744A | 2008-11-06 |
Attorney, Agent or Firm:
OGASAWARA PATENT OFFICE (JP)
Patent business corporation Ogasawara patent firm (JP)
Patent business corporation Ogasawara patent firm (JP)
Download PDF: