Title:
THREE-DIMENSIONAL STACKED FAN-OUT PACKAGE STRUCTURE AND PREPARATION METHOD THEREFOR
Document Type and Number:
WIPO Patent Application WO/2024/045758
Kind Code:
A1
Abstract:
A three-dimensional stacked fan-out package structure and a preparation method therefor. The fan-out package structure sequentially comprises chip stacks, a silicon interposer (101), transmission chips (122), a coating layer (102) and a substrate (302) from top to bottom. Electrical connection between the silicon interposer (101) and the substrate (302) is implemented by providing a rewiring layer (103) or metal solder balls (311), so as to perform signal transmission. The transmission chips (122) are provided on the lower surface of the silicon interposer (101), and the chip stacks comprising a plurality of chips are provided on the upper surface of the silicon interposer (101).
Inventors:
CHEN YENHENG (CN)
LIN CHENGCHUNG (CN)
YANG JIN (CN)
LIN CHENGCHUNG (CN)
YANG JIN (CN)
Application Number:
PCT/CN2023/099289
Publication Date:
March 07, 2024
Filing Date:
June 09, 2023
Export Citation:
Assignee:
SJ SEMICONDUCTOR JIANGYIN CORP (CN)
International Classes:
H01L25/18; H01L21/50; H01L21/56; H01L23/31; H01L23/367
Foreign References:
| CN216413054U | 2022-04-29 | |||
| CN114171469A | 2022-03-11 | |||
| CN115101519A | 2022-09-23 | |||
| CN107564825A | 2018-01-09 | |||
| US20180190635A1 | 2018-07-05 |
Attorney, Agent or Firm:
J.Z.M.C. PATENT AND TRADEMARK LAW OFFICE (GENERAL PARTNERSHIP) (CN)
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