Title:
TIME DELAY CIRCUIT AND MEMORY
Document Type and Number:
WIPO Patent Application WO/2023/221230
Kind Code:
A1
Abstract:
Disclosed in embodiments of the present disclosure are a time delay circuit and a memory. The time delay circuit comprises: a self-shielding module and a time delay module. The self-shielding module is configured to receive an initial command signal and N initial clock signals, register the initial command signal according to a first initial clock signal, which first triggers the initial command signal, among the N initial clock signals, shield other N-1 second initial clock signals among the N initial clock signals, and output N intermediate command signals, wherein N is an integer greater than or equal to 2, and the N initial clock signals have identical frequencies and different phases; the time delay module is electrically connected to the self-shielding module, and is configured to receive the N intermediate command signals and the N initial clock signals and perform time delay output on the N intermediate command signals to obtain time delay command signals. According to the present disclosure, the accuracy of signal processing can be improved.
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Inventors:
LU TIANCHEN (CN)
Application Number:
PCT/CN2022/100189
Publication Date:
November 23, 2023
Filing Date:
June 21, 2022
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
H03K5/00
Foreign References:
| JP2004247771A | 2004-09-02 | |||
| CN109450545A | 2019-03-08 | |||
| CN106712747A | 2017-05-24 | |||
| CN104079267A | 2014-10-01 | |||
| US20070288184A1 | 2007-12-13 | |||
| US20190086949A1 | 2019-03-21 |
Attorney, Agent or Firm:
CHINA PAT INTELLECTUAL PROPERTY OFFICE (CN)
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