TECHNICAL FIELD

The disclosure relates to a system comprising transimpedance amplifier circuit. The disclosure further relates to a device comprising the system.

BACKGROUND

A transimpedance amplifier (TIA) is current measurement device that converts a typically weak input current signal to an output voltage of considerable magnitude.

One common application for a TIA is in an optical communication receiver. An optical sensor (e.g. a photodiode) converts input light into an electrical current signal and presents it at the input of the TIA. The TIA converts this electrical current signal into an output voltage having some gain, commonly referred to as transimpedance gain, and this signal is further processed by other stages. TIAs can be used in a variety of applications and their usage is not limited to optical sensing applications.

A known transimpedance amplifier circuit 100 is shown in Figure 1a which is commonly referred to as a shunt feedback TIA. Here the optical sensor is modelled as a current source Ip and a capacitor C. In order to achieve an amplifier with a gain bandwidth product (GBW) of greater than 100MHz, for optical communication in the range of tens of MHz (the bandwidth of the TIA) a high quiescent current Iq of 5-10mA is typically required.

Another known transimpedance amplifier circuit 150 is shown in Figure 1b which is an inverter TIA with resistive feedback. Higher bandwidth with low power is achievable compared to the known transimpedance amplifier circuit 100 is shown in Figure 1a. Higher gain is achievable with increasing the number of stages, at the cost of compromising stability. Due to the absence of biasing circuitry in the known transimpedance amplifier circuit 150, the quiescent current l _q and gain have high process voltage temperature (PVT) variation.

It is therefore an aim of the present disclosure to provide a transimpedance amplifier circuit that address one or more of the problems above or at least provides a useful alternative. SUMMARY

In general, this disclosure proposes to overcome the above problems by providing a trans impedance amplifier circuit based on a common gate input stage with local feedback to offer a low impedance path to the input current (which may for example be a photo-generated current in embodiments where an optical sensor converts light into an input current signal).

The common gate input stage with a fast loop facilitates providing smaller input impedance without increasing the current consumption to increase the transconductance (gm) of the trans-impedance amplifier circuit, and thereby reduce the quiescent current l _q.

In particular, to address the same applications as the known solutions discussed above, for optical communication in the range of tens of MHz, embodiments of the present disclosure offer low impedance to the optical sensor through a fast loop which reduces the power consumption with the quiescent current l _q being approximately 100pA.

Thus the transimpedance amplifier circuit is able to sense pulses of light in the tens of MHz data-rate rejecting ambient light and pulses amplitude variations within a power budget of less than 180uW, making it suitable for optical communication between handheld/wearable devices.

According to one aspect of the present disclosure there is provided a system comprising a transimpedance amplifier circuit, the transimpedance amplifier circuit comprising: a primary transimpedance circuit stage for connection to an optical sensor, wherein the primary transimpedance circuit stage comprises: a first current source controlled by a first input bias voltage; a first transistor, a second transistor and a first resistor which provide a current path through the first transistor and the first resistor for current to flow through the primary transimpedance circuit stage in response to light being sensed by the optical sensor, wherein a gate terminal of the first transistor is coupled to a first output terminal arranged to supply a first output voltage and a gate terminal of the second transistor receives a second input bias voltage; and a second current source, wherein the first current source and the second current source provide biasing currents for the primary transimpedance circuit stage. The transimpedance amplifier circuit further comprises: a secondary transimpedance circuit stage coupled to the primary transimpedance circuit stage via a third transistor and a second resistor, wherein the secondary transimpedance circuit stage comprises: a third current source controlled by the first input bias voltage; a fourth transistor, a fifth transistor and a third resistor which provide a current path through the fourth transistor and the third resistor for current to flow through the secondary transimpedance circuit stage in response to light being sensed by the optical sensor, wherein a gate terminal of the fourth transistor is coupled to a second output terminal arranged to supply a second output voltage which has opposite polarity with respect to the first output voltage, and a gate terminal of the fifth transistor receives the second input bias voltage; and a fourth current source, wherein the third current source and the fourth current source provide biasing currents for the secondary transimpedance circuit stage.

The first current source may comprise a sixth transistor and a fourth resistor, wherein a gate terminal of the sixth transistor is arranged to receive the first input bias voltage.

The second current source may be a resistor.

By copying and injecting the sensed input current into the secondary transimpedance circuit stage, pseudo differential signal output voltages can be generated at the first and second output terminals (vpre-, vpre+). By doubling the effective input signal that is supplied to a later circuit stage (e.g. a comparator), increased signal-to-noise ratio (SNR) is achieved.

The dominant pole of the transimpedance amplifier circuit is at the first output terminal which supplies the first output voltage, therefore parasitic capacitance of the photodiode plays a secondary role on the system bandwidth.

The third current source may comprise a seventh transistor and a fifth resistor, wherein a gate terminal of the seventh transistor is arranged to receive the first input bias voltage.

The fifth resistor may be a variable resistor. This advantageously enables the resistance of the second resistor to be varied in order to create a DC offset voltage which corresponds to the input signal and trim against mismatch so that the first and second output voltage signals cross each other at a mid-point.

The fourth current source may be a resistor. The fourth current source may be a variable resistor. This advantageously enables the resistance of the variable resistor to be varied in order to create a DC offset voltage which corresponds to the input signal and trim against mismatch so that the first and second output voltage signals cross each other at a mid-point.

A gate terminal of the third transistor may be coupled to the first output terminal.

The transimpedance amplifier circuit may further comprise a bias circuit arranged to receive a reference voltage and provide the first input bias voltage and the second input bias voltage.

The bias circuit may comprises a voltage amplifier arranged to receive a reference voltage as an input, wherein an output of the voltage amplifier is coupled to a gate terminal of a first biasing transistor that is connected in series with a resistor and a second biasing transistor, a gate terminal of the second biasing transistor coupled to a first filter providing the first input voltage, wherein the output of the voltage amplifier is coupled to a second filter providing the second input voltage.

Negative feedback control of the voltage amplifier sets the required bias voltages (the first and second input bias voltages). Since this loop is providing only the biasing conditions, which are first order static, the bandwidth of this loop can be slow independent from the communication data rate (tens of MHz). Therefore, the bias circuit consumes less power and its noise contribution is highly filtered by the first filter and the second filter.

In embodiments whereby the transimpedance amplifier circuit comprises both a primary transimpedance circuit stage and a secondary transimpedance circuit stage, the system may further comprise a comparator arranged to receive the first output voltage and the second output voltage, the comparator configured to: output a first supply voltage if the second output voltage is greater than the first output voltage; and output a second supply voltage if the second output voltage is less than the first output voltage, the first supply voltage greater than the second supply voltage.

In embodiments whereby the transimpedance amplifier circuit comprises both a primary transimpedance circuit stage and a secondary transimpedance circuit stage, the system may further comprise a correction circuit, the correction circuit comprising: an error amplifier; a first sample and hold stage arranged to sample the first output voltage when the comparator outputs the first supply voltage, and provide the sample of the first output voltage as an input to the error amplifier; a second sample and hold stage arranged to sample the second output voltage when the comparator outputs the second supply voltage, and provide the sample of the second output voltage as an input to the error amplifier; wherein the error amplifier is configured to sink or source current in the transimpedance amplifier circuit that is related to the difference between the sample of the first output voltage and the sample of the second output voltage.

Thus the correction circuit provides a correction loop to compensate for the offset changes due to the ambient light or signal level. The correction loop acts in a way to equalize the peaks of the first and second output voltage signals by sinking or sourcing current related to the difference of the sampled values of the first and second output voltage signals. Therefore, the first and second output voltage signals cross each other at the mid-point which facilitates (i) finding the optimum threshold for the comparator response and jitter, (ii) achieving 50% duty cycle at the voltage signal output by the comparator; and (iii) rejection of the impact of ambient light during transmission.

The system may further comprise the optical sensor. The optical sensor may be a photodiode.

According to one aspect of the present disclosure there is provided a device comprising the system described herein.

These and other aspects will be apparent from the embodiments described in the following. The scope of the present disclosure is not intended to be limited by this summary nor to implementations that necessarily solve any or all of the disadvantages noted.

Brief Description of the Drawings

Some embodiments of the disclosure will now be described by way of example only and with reference to the accompanying drawings, in which:

Figures 1a and 1b illustrate known transimpedance amplifier circuits;

Figure 2 is a system according to an embodiment of the present disclosure;

Figures 3a and 3b illustrates a transimpedance amplifier circuit according to an embodiment of the present disclosure;

Figure 3c illustrates a transimpedance amplifier circuit according to an alternative embodiment of the present disclosure;

Figure 4 illustrates an example bias circuit for use with the transimpedance amplifier circuit shown in Figures 3a and 3b;

Figure 5 shows example transimpedance amplifier circuit waveforms;

Figure 6 shows the system comprising a correction circuit; Figure 7 shows example transimpedance amplifier circuit waveforms in the presence of ambient light;

Figure 8 shows example transimpedance amplifier circuit waveforms in the presence of ambient light with the correction circuit disabled;

Figure 9 shows example transimpedance amplifier circuit waveforms in the presence of ambient light with the correction circuit enabled; and Figure 10 is a schematic block diagram of a device.

Detailed Description

Specific embodiments will now be described with reference to the drawings.

Reference is first made to Figure 2 which illustrates a system 200 according to one embodiment of the present disclosure.

As shown in Figure 2, the system 200 comprises an optical sensor 202 which converts light which is incident on a photon sensitive area of the optical sensor 202 into an electrical current signal. The optical sensor 202 may for example be a photodiode but other forms of optical sensor 202 may also be used in the system 200.

The optical sensor 202 is coupled to an input node (IN) of the transimpedance amplifier circuit 204. The optical sensor 202 outputs a current signal to a transimpedance amplifier circuit 204 which converts the input current into a first output voltage and a second output voltage which is the inverse (has opposite polarity) of the first output voltage.

The optical sensor 202 may be integrated into the same die on which the transimpedance amplifier circuit 204 sits, alternatively the optical sensor 202 may be external to the die comprising the transimpedance amplifier circuit 204.

One example implementation of the transimpedance amplifier circuit 204 is shown in Figure 3a.

As shown in Figure 3a, the transimpedance amplifier circuit 204 comprises a primary transimpedance circuit stage 302 connected to the optical sensor 202, and may optionally further comprise a secondary transimpedance circuit stage 304 that is coupled to the primary transimpedance circuit stage 302. The primary transimpedance circuit stage 302 comprises a first current source 300 that is controlled by a first input bias voltage (Vbiasl). The first current source 300 is connected to a positive supply voltage Vdd (which may for example be 1.8V).

The primary transimpedance circuit stage 302 further comprises a first transistor 314, a second transistor 308 and a first resistor 316 that offers a small input impedance and provides a current path 340 for current to flow through the first transistor 314 and the first resistor 316 in response to light being sensed by the optical sensor 202.

A gate terminal of the first transistor 314 is coupled to a first output terminal arranged to supply a first output voltage (Vpre-). In the example, implementation shown in Figure 3a, the first transistor 314 is a p-type transistor with its source terminal is connected to the first resistor 316 and its drain terminal connected to the optical sensor 202. The first resistor 316 is connected to the positive supply voltage, Vdd.

A gate terminal of the second transistor 308 is arranged to receive a second input bias voltage (Vbias2). In the example implementation shown in Figure 3a, the second transistor 308 is an n-type transistor with its source terminal connected to the optical sensor 202 and its drain terminal is connected to the first output terminal. Thus, the drain terminal of the second transistor 308 is connected to the gate terminal of the first transistor 314.

The primary transimpedance circuit stage 302 further comprises a second current source 312. In the example implementation shown in Figure 3a the second current source 312 is shown as a resistor however it will be appreciated that this may be implemented in other ways. The second current source 312 is connected between the source terminal of the second transistor 308 and ground.

The second transistor 308 is part of a common gate input stage and a fast loop is form by the first transistor 314 and the second transistor 308 in the primary transimpedance circuit stage 302 to offer a low impedance path to the input current.

The first current source 300 and the second current source 312 provide biasing currents for the primary transimpedance stage 302.

In some embodiments, a secondary transimpedance circuit stage 304 is coupled to the primary transimpedance circuit stage 302 via a third transistor 318 and a second resistor 320. The gate terminal of the third transistor 318 is coupled to the first output terminal that supplies the first output voltage (Vpre-). In the example implementation shown in Figure 3a, the third transistor 318 is a p-type transistor with its source terminal connected to the second resistor 320. The second resistor 320 is connected between the source terminal of the third transistor 318 and the positive supply voltage, Vdd.

The third transistor 318 and the second resistor 320 mirrors and injects the signal current (that flows on current path 340 in response to light being sensed by the optical sensor) to the secondary transimpedance circuit stage 304.

The secondary transimpedance circuit stage 304 comprises a fourth transistor 330 a fifth transistor 324 and a third resistor 332 which forms a fast loop offering a low impedance path to the input current and provides a current path 360 through the fourth transistor 330 and the third resistor 332 for this injected current to flow through the secondary transimpedance circuit stage in response to light being sensed by the optical sensor 202.

A gate terminal of the fourth transistor 330 is coupled to a second output terminal that is arranged to supply a second output voltage (Vpre+) which has opposite polarity with respect to the first output voltage (Vpre-). In the example implementation shown in Figure 3a, the fourth transistor 330 is a p-type transistor with its source terminal connected to the third resistor 332 and its drain terminal connected to the drain terminal of the third transistor 318. The third resistor 332 is connected to the positive supply voltage, Vdd.

A gate terminal of the fifth transistor 324 receives the second input bias voltage (Vbias2). In the example implementation shown in Figure 3a, the fifth transistor 324 is an n-type transistor with its source terminal connected to the drain terminals of the third transistor 318 and the fourth transistor 330.

The secondary transimpedance circuit stage 304 further comprises a third current source 350 that is controlled by a first input bias voltage (Vbiasl). The third current source 300 is connected to the positive supply voltage Vdd.

The secondary transimpedance circuit stage 304 further comprises a fourth current source 328 that is connected between the source terminal of the fifth transistor 324 and ground. In the example implementation shown in Figure 3a the fourth current source 328 is shown as a variable resistor, however it will be appreciated that this may be implemented in other ways. The third current source 350 and the fourth current source 328 provide biasing currents for the secondary transimpedance circuit stage 304.

Figure 3b illustrates example components of the first current source 300 and the third current source 350.

As shown in Figure 3b the first current source 300 may comprise a sixth transistor 306 and a fourth resistor 310, wherein a gate terminal of the sixth transistor 306 is arranged to receive the first input bias voltage (Vbiasl). The sixth transistor 306 may be a p-type transistor, wherein a source terminal of the sixth transistor is coupled to the fourth resistor 310 and a drain terminal of the sixth transistor 306 is coupled to the first output terminal that supplies the first output voltage (Vpre-). The fourth resistor 310 is connected between the source terminal of the sixth transistor 306 and the positive supply voltage, Vdd. It will be appreciated that other arrangements for the first current source 300 are possible other than the one shown in Figure 3b.

As shown in Figure 3b the third current source 350 may comprise a seventh transistor 322 and a fifth resistor 326, wherein a gate terminal of the seventh transistor 322 is arranged to receive the first input bias voltage (Vbiasl). The seventh transistor 322 may be a p-type transistor, wherein a source terminal of the sixth transistor is coupled to the fifth resistor 326 and a drain terminal of the seventh transistor 322 is coupled to the second output terminal that supplies the second output voltage (Vpre+). The fifth resistor 326 is connected between the source terminal of the seventh transistor 322 and the positive supply voltage, Vdd. The fifth resistor 326 may be a variable resistor. It will be appreciated that other arrangements for the third current source 350 are possible other than the one shown in Figure 3b.

Whilst Figures 3a and 3b shows the second transistor 308 and the fifth transistor 324 as n- type transistors and the remaining transistors as p-type transistors it will be appreciated this is merely an example and the transimpedance amplifier circuit 204 can operate in the same way with the arrangement flipped as shown in Figure 3c. In the arrangement of Figure 3c, the second transistor 308 and the fifth transistor 324 are p-type transistors and the remaining transistors are n-type transistors.

In operation, the current flowing on current path 340 through the first transistor 314 and the first resistor 316 in response to light being sensed by the optical sensor 202 causes the first output voltage (Vpre-) on the first output terminal to transition from a high voltage level to a low voltage level. Conversely, the current flowing on current path 360 through the fourth transistor 330 and the third resistor 332 in response to light being sensed by the optical sensor 202 causes the second output voltage (Vpre+) on the second output terminal to transition from the low voltage level to the high voltage level.

Figures 3a-c show the transimpedance amplifier circuit 204 comprising both a primary transimpedance circuit stage 302 and a secondary transimpedance circuit stage 304 in order to have a pseudo differential output.

In some embodiments, the transimpedance amplifier circuit 204 comprises only one of these stages i.e. the transimpedance amplifier circuit 204 may provide only the first output voltage (Vpre-) or the second output voltage (Vpre+). In comparison to embodiments where pseudo differential signal output voltages are generated, such embodiments will provide poorer SNR and power supply rejection, which may still be acceptable for some applications with the advantage of reduced number of components and thus smaller circuit size and power consumption. These embodiments are described in more detail below.

Figure 4 illustrates an example bias circuit 400 which may be used to generate the first input bias voltage (Vbiasl) and the second input bias voltage (Vbias2) which are provided as inputs to the transimpedance amplifier circuit 204. The bias circuit 400 shown in Figure 4 is appropriate for the transimpedance amplifier circuit shown in Figures 3a and 3b. It will be appreciated that the bias circuit 400 would need to be flipped in order to be suitable for the transimpedance amplifier circuit shown in Figure 3c.

The bias circuit 400 shown in Figure 4 comprises a voltage amplifier 402 arranged to receive a reference voltage (Vref) at its positive input.

The output of the voltage amplifier 402 is coupled to a gate terminal of a first biasing transistor 404 that is connected in series with a resistor 406 and a second biasing transistor 408. The first biasing transistor 404 may be an n-type transistor with its source terminal connected to the resistor 406 and its drain terminal connected to the second biasing transistor 408. The resistor 406 is connected between the first biasing transistor 404 and ground. Negative feedback is provided by way of the source terminal of the first biasing transistor 404 being connected to the negative input of the voltage amplifier 402.

A gate terminal of the second biasing transistor 408 is coupled to a first filter formed of resistor 412 and capacitor 414 connected to the positive supply voltage, Vdd, the first filter providing the first input bias voltage (Vbiasl). The output of the voltage amplifier 402 is coupled to a second filter formed of a resistor 416 and a capacitor 418 connected to ground, the second filter providing the second input bias voltage (Vbias2)

As shown in Figure 4, the second biasing transistor 408 may be a p-type transistor with its source terminal connected to a resistor 410 and its drain terminal connected to the first biasing transistor 404. The resistor 410 is connected between the second biasing transistor 408 and the positive supply voltage, Vdd.

The negative feedback loop configuration sets the voltage value at the negative input of the voltage amplifier 402 (source terminal of the first transistor) equal to the reference voltage (Vref) that it received at the positive input of the voltage amplifier 402. Therefore, the current on the bias branch (formed by the resistor 410, the second biasing transistor 408 and the first biasing transistor 404) will be set by the ratio of the reference voltage (Vref) and resistor 406 and the voltages on the gate terminals of the sixth transistor 306 and the second transistor 308 of the bias branch accordingly.

It will be appreciated that the bias circuit 400 shown in Figure 4 is merely an example, and the first input bias voltage (Vbiasl) and the second input bias voltage (Vbias2) may be generated by any highly filtered bias circuit which ultimately controls the voltages and currents in the transimpedance amplifier circuit 204.

Referring back to Figure 2, the output of the transimpedance amplifier circuit 204 is coupled to a comparator 206.

In embodiments, whereby the transimpedance amplifier circuit 204 comprises both a primary transimpedance circuit stage 302 and a secondary transimpedance circuit stage 304, the transimpedance amplifier circuit 204 supplies the first output voltage (Vpre-) and the second output voltage (Vpre+) to the comparator 206 which provides an output voltage (Vout). In particular, the first output voltage (Vpre-) and the second output voltage (Vpre+) are pseudo fully-differential signals used at the input of the comparator 206.

In operation, the comparator 206 is configured to output the positive supply voltage, Vdd, if the second output voltage (Vpre+) is greater than the first output voltage (Vpre-), and output Ov (ground) if the second output voltage (Vpre+) is less than the first output voltage (Vpre-). In embodiments, whereby the transimpedance amplifier circuit 204 comprises only a single transimpedance circuit stage, the transimpedance amplifier circuit 204 supplies a single output voltage, the first output voltage (Vpre-) or the second output voltage (Vpre+), as an input to the comparator 206 which also receives a fixed reference voltage. In operation, if the second output voltage (Vpre+) is supplied to the comparator 206, the comparator 206 is configured to output the positive supply voltage, Vdd, if the second output voltage (Vpre+)is greater than the fixed reference voltage, and output Ov (ground) if the second output voltage (Vpre+) is less than the fixed reference voltage. If the first output voltage (Vpre-) is supplied to the comparator 206, the comparator 206 is configured to output the positive supply voltage, Vdd, if the first output voltage (Vpre-) is less than the fixed reference voltage, and output Ov (ground) if the first output voltage (Vpre-) from is greater than the fixed reference voltage.

In these embodiments, the correction circuit implements a DC correction loop to equalize the DC level of the output voltage signal (Vpre- or Vpre+) to the reference voltage by sourcing or sinking correction current (lpk_pk) into the transimpedance amplifier circuit 204. The error amplifier610 is configured to source or sink current (lpk_pk) into the transimpedance amplifier circuit 204 that is related to the difference between the DC level of the output voltage (Vpre- or Vpre+) and the reference voltage.

Figure 5 shows example waveforms of the transimpedance amplifier circuit 204.

Waveform 502 corresponds to the photodetector current that is provided as an input to the transimpedance amplifier circuit 204 and flows on current path 340 and current path 360. The square wave shape is a result of pulses of light (communication bits) being incident on the optical sensor 202 (e.g. transmitted through an optical communication link), wherein the photodetector current increases when light is incident on the optical sensor 202.

Waveform 504 corresponds to the first output voltage (Vpre-) on the first output terminal. As shown in Figure 5, in response to the rising edge of the photodetector current 502, the first output voltage (Vpre-) 504 decreases from a high voltage level to a low voltage level. In response to the falling edge of the photodetector current 502, the first output voltage (Vpre-) 504 increases from the low voltage level to the high voltage level.

Waveform 506 corresponds to the second output voltage (Vpre+) on the second output terminal. As shown in Figure 5, in response to the rising edge of the photodetector current 502, the second output voltage (Vpre+) 506 increases from a low voltage level to a high voltage level. In response to the falling edge of the photodetector current 502, the second output voltage (Vpre+) 506 decreases from the high voltage level to the low voltage level.

The first output voltage (Vpre-) and second output voltage (Vpre+) signals are fed to the comparator 206, and they are digitized as an output voltage signal (Vout) that is output by the comparator 206. Waveform 508 corresponds to the digital output voltage signal (Vout) that is output by the comparator 206.

As shown in Figure 5, the comparator 206 outputs the positive supply voltage, Vdd, when the second output voltage (Vpre+) 506 is greater than the first output voltage (Vpre-) 504, and outputs Ov (ground) when the second output voltage (Vpre+) 506 is less than the first output voltage (Vpre-) 504.

As shown in Figure 5, a 12Mbit rate communication can be accomplished with approximately 35ns of delay between the the rising edge of the photodetector current 502 being reflected at the output of the comparator 206 with the digital output voltage signal (Vout) rising from Ov (ground) to the positive supply voltage, Vdd. It will be appreciated that this delay will vary in dependence on many different circuit design parameters and also the input signal.

In embodiments, whereby the transimpedance amplifier circuit 204 comprises both a primary transimpedance circuit stage 302 and a secondary transimpedance circuit stage 304, the system 200 may further comprise a correction circuit 600, which is shown in Figure 6. The correction circuit 600 advantageously, rejects the impact of ambient light during transmission and provides immunity to signal amplitude drift over time.

As shown in Figure 6, the correction circuit 600 comprises an error amplifier 610, a first sample and hold stage, a second sample and hold stage, and a controller 601.

The controller 601 monitors the digital output voltage signal (Vout) and controls the first sample and hold stage and second sample and hold stage in dependence on the digital output voltage signal (Vout). The functionality of the correction circuit 600 can be enabled by transmission of a suitable enable control signal to the controller 601 (not shown in Figure 6). Similarly, the functionality of the correction circuit 600 can be disabled by transmission of a suitable disable control signal to the controller 601 (not shown in Figure 6).

The first sample and hold stage is formed of a resistor 602, a switch S1 and a capacitor 604. The first sample and hold stage receives the first output voltage (Vpre-) from the transimpedance amplifier circuit 204. The controller 601 is configured to control the switch S1 of the first sample and hold stage (using control signal Smpl-) to take a sample of the first output voltage (Vpre-) when the first output voltage (Vpre-) is high (i.e. when the digital output voltage signal (Vout) is low). This sampled voltage is stored by the capacitor 604 and provided as an input to the error amplifier 610.

The second sample and hold stage is formed of a resistor 606, a switch S2 and a capacitor 608. The second sample and hold stage receives the second output voltage (Vpre+) from the transimpedance amplifier circuit 204. The controller 601 is configured to control the switch S2 of the second sample and hold stage (using control signal Smpl+) to take a sample of the second output voltage (Vpre+) when the second output voltage (Vpre+) is high (i.e. when the digital output voltage signal (Vout) is high). This sampled voltage is stored by the capacitor 608 and provided as a further input to the error amplifier 610.

The correction circuit 600 implements a peak detector correction loop to equalize the peaks of the first and second output voltage signals by sourcing or sinking current (lpk_pk) into the transimpedance amplifier circuit 204. The error amplifier 610 is configured to source or sink current (lpk_pk) into the transimpedance amplifier circuit 204 that is related to the difference between the sample of the first output voltage (Vpre-) and the sample of the second output voltage (Vpre+).

The output of the error amplifier 610 may be coupled to the transimpedance amplifier circuit 204 in different ways.

The output of the error amplifier 610 may be coupled to the secondary transimpedance circuit stage 304. Referring back to Figures 3a-c, the output of the error amplifier 610 may be coupled to the third transistor 318, the fourth transistor 330, and the fifth transistor 324. In particular, the output of the error amplifier 610 may be coupled to the drain terminal of the third transistor 318, the drain terminal of the fourth transistor 330, and the source terminal of the fifth transistor 324.

As an alternative (not shown in Figures 3a-c) the output of the error amplifier 610 may be coupled to the primary transimpedance circuit stage 302. In these implementations the output of the error amplifier 610 is coupled to the input node (IN) of the transimpedance amplifier circuit 204. That is, the error amplifier 610 is coupled to the first transistor 314 and the second transistor 308. In particular, the error amplifier 610 is coupled to the drain terminal of the first transistor 314 and the source terminal of the second transistor 308. Figure 7 shows example waveforms of the correction circuit 600 when the correction current (lpk_pk) is coupled to the secondary transimpedance circuit stage 304 as shown in Figure 3a- c.

Ambient light results in an additional DC current from optical sensor 202 at the input node (IN) of the transimpedance amplifier circuit 204. When there is additional DC current, the peak level of the first output voltage (Vpre-) will decrease (since there will be additional drop on resistor 316 and the first transistor 314 due to it being a PMOS transistor) in order to supply that additional current as well.

The additional DC current due to ambient light is injected into the secondary transimpedance circuit stage 304 via the third transistor 318 and the resistor 320 in the opposite direction. Therefore, if there is no correction performed by the correction circuit 600 the second output voltage (Vpre+) will increase in the same amount, this scenario is illustrated in Figure 8.

When there is correction performed by the correction circuit 600 the peak to peak loop compensates for this by sinking/sourcing current (lpk_pk) so that the DC level of the second output voltage (Vpre+) can track the DC level of the first output voltage (Vpre-).

In implementations whereby the output of the error amplifier 610 is coupled to the secondary transimpedance circuit stage 304, when the peak level of the first output voltage (Vpre-) decreases due to an increase of ambient light, the correction circuit 600 supplies a sink current (lpk_pk) to decrease the DC level, hence the peak level, of the second output (Vpre+) with no effect on the first output voltage (Vpre-).

Therefore, as shown in Figure 7, when the correction loop is enabled, both the peak level of the first output voltage (Vpre-) and the peak level of the second output voltage (Vpre+) decrease due to the increase of ambient light.

In implementations whereby the output of the error amplifier 610 is coupled to the primary transimpedance circuit stage 302, the correction circuit 600 supplies a source current (lpk_pk) to prevent the DC level, hence the peak level, of the first output (Vpre-) from decreasing.

The system 200 according to embodiments of the present disclosure may employ an AC coupling capacitor at the input of the transimpedance amplifier circuit 204. Such an AC coupling capacitor will not only extract and reject the DC information of ambient light but also the information related to the input signal amplitude, but it has a settling time related to the RC time constant of the AC coupling capacitor. This can be problematic in case of the lack of communication the information related to the signal amplitude will be lost with the RC time constant and would need to be recovered again when communication starts. If the communication protocol cannot handle the waiting for the resettling of the AC coupling capacitor this would cause loss of data. The peak detector loop of the correction circuit 600 is a sampled system unlike AC coupling, therefore in case of the absence of signal the ambient light and signal level information is not lost but held in the sampling capacitors 604 and 608 of the correction circuit 600. With this feature, the peak detector loop can overcome the preamble requirement of the AC coupling solution in order to reject the ambient light.

If the correction circuit 600 is enabled the peak detector loop of the correction circuit 600 continuously works in order to minimize the difference between the sampled values of the first output voltage (Vpre-) and the second output voltage (Vpre+)

In the event of no more communication bits, then the digital output voltage signal (Vout) will no longer toggle anymore, which means no more sampling will be performed by the correction circuit 600. In this scenario, the correction circuit 600 continues injecting current according to the latest sampled values since the information related to the signal value and ambient light will be stored in the sampling capacitors 604,608.

Figure 7 further illustrates the sampling of the first output voltage (Vpre-) using the switch S1 when the first output voltage (Vpre-) is high, and the sampling of the second output voltage (Vpre+) using the switch S2 when the second output voltage (Vpre+) is high.

Figure 8 illustrates example waveforms of the transimpedance amplifier circuit 204 in the presence of ambient light when the correction circuit 600 is disabled.

In the presence of ambient light, the input current at the input node (IN) of the transimpedance amplifier circuit 204 will have a DC component and this DC component will also be converted to voltage on the first output voltage (Vpre-) and the second output voltage (Vpre+) signals.

Due the shifted DC values of the first output voltage (Vpre-) and the second output voltage (Vpre+) signals they will not cross each other anymore which causes the output of the comparator 206 to saturate as shown by the digital output voltage signal (Vout) shown in Figure 8. Figure 9 illustrates example waveforms of the transimpedance amplifier circuit 204 in the presence of ambient light when the correction circuit 600 is enabled.

In this scenario, the peak detector loop of the the correction circuit 600 will try to equalize the peaks of the first output voltage (Vpre-) and the second output voltage (Vpre+) signals, therefore the second output voltage (Vpre+) will follow the first output voltage (Vpre-). As discussed above, the DC component on the first output voltage (Vpre-) due to the ambient light will be sensed and replicated for the second output voltage (Vpre+).

Since the second output voltage (Vpre+) can follow the changes on first output voltage (Vpre- ) they will continue crossing each-other and the comparator output will not saturate.

Figure 9 illustrates the input current at the transimpedance amplifier circuit 204, artefacts 904 on the first output voltage (Vpre-) 504, artefacts 906 on the second output voltage (Vpre+) 506, and the digital output voltage signal (Vout) that is output by the comparator 206. These are artefacts due to the sampling instance, when closing and opening of the switches S1 and S2 which are not ideal (they are implemented as transistors) these effects are known as charge injection and clock feedthrough. As long as the artefacts are symmetrical for both the first output voltage (Vpre-) 504 and the second output voltage (Vpre+) 506 they cancel each other out.

Figure 10 illustrates a computing device 10 comprising the system 200 according to any of the embodiments described herein. The computing device 10 shown in Figure 10 may be a mobile phone, a tablet device, a laptop computer, a gaming device or any other type of computing device (whether mobile or not) For example, the computing device 10 may be a wearable device (e.g. a smartwatch or headset).

Embodiments of the present disclosure achieve a transimpedance amplifier suitable for optical communication in the range of tens of MHz with the quiescent current l _q being only approximately 100pA with a required power supply of only 1.8V, whilst the known transimpedance amplifier circuit shown in Figures 1a and 1b require a quiescent current lq of approximately 5-10mA for this application.

Whilst embodiments have been described with reference to an optical sensor 202 being coupled to the transimpedance amplifier circuit 204, it will be appreciated that any other component, circuit, or system that delivers an output current may be coupled to the transimpedance amplifier circuit 204. Although the disclosure has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in any embodiments, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.

List of Reference Numerals

10 device

100 known transimpedance amplifier circuit

150 known transimpedance amplifier circuit

200 system

202 optical sensor

204 transimpedance amplifier circuit

206 comparator

300 first current source

302 primary transimpedance circuit stage

304 secondary transimpedance circuit stage

306 sixth transistor

308 second transistor

310 fourth resistor

312 second current source

314 first transistor

316 first resistor

318 third transistor

320 second resistor

322 seventh transistor

324 fifth transistor

326 fifth resistor

328 fourth current source

330 fourth transistor third resistor current path third current source current path bias circuit voltage amplifier first biasing transistor resistor second biasing transistor resistor first filter resistor first filter capacitor second filter resistor second filter capacitor photodetector current first output voltage second output voltage digital output voltage correction circuit controller resistor capacitor resistor capacitor error amplifier artefacts on the first output voltage artefacts on the second output voltage