TRENCH DMOS DEVICE WITH IMPROVED DRAIN CONTACT

Title:

TRENCH DMOS DEVICE WITH IMPROVED DRAIN CONTACT

Document Type and Number:

WIPO Patent Application WO2003038863

Kind Code:

A3

Abstract:

A trench DMOS transistor device that comprises: (a) a substrate (200) of a first conductivity type; (b) an epitaxial layer (202) of first conductivity type over the substrate, wherein the epitaxial layer has a lower majority carrier concentration than the substrate; (c) a trench extending into the epitaxial layer from an upper surface of the epitaxial layer; (d) an insulating layer (210) lining at least a portion of the trench; (e) a conductive region (211) within the trench adjacent the insulating layer; (f) a body region of a second conductivity type provided within an upper portion of the epitaxial layer and adjacent the trench; (g) a source region of first conductivity type within an upper portion of the body region and adjacent the trench; and (h) one or more low resistivity deep regions (219) extending into the device from an upper surface of the epitaxial layer. The low resistivity deep region acts to provide electrical contact with the substrate, which is a common drain region for the device. By constructing a trench DMOS transistor device in this fashion, source, drain and gate contacts can all be provided on a single surface of the device.

Inventors:

HSHIEH FWU-LUAN
SO KOON CHONG
NELSON WILLIAM JOHN
AMATO JOHN E

Application Number:

PCT/US2002/034826

Publication Date:

November 20, 2003

Filing Date:

October 30, 2002

Export Citation:

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Assignee:

GEN SEMICONDUCTOR INC (US)

International Classes:

H01L21/336; H01L27/088; H01L29/78; H01L21/8234; H01L29/417; (IPC1-7): H01L29/76; H01L29/94; H01L31/062; H01L31/113; H01L31/119

Foreign References:

US5925911A	1999-07-20
US5463241A	1995-10-31
US5072266A	1991-12-10

Other References: