VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE AND MEMORY CELL FORMATION METHOD

WIPO Patent Application WO/2010/021134

A1

A memory cell (300) is configured so that it is equipped with a semiconductor substrate (301); a variable resistance element (309) that consists of a lower electrode (309a), an upper electrode (309c), and a variable resistance layer (309b), the resistance value of which reversibly changes based on the application of voltage signals of different polarities across the two electrodes; and an N-type MOS transistor (317) configured on the main surface of the semiconductor substrate (301), wherein the variable resistance layer (309b) comprises an oxygen-depleted transition metal oxide layer (309b-1) that contacts the lower electrode (309a) and is composed of MOx, and an oxygen-depleted transition metal oxide layer (309b-2) that contacts the upper electrode (309c) and is composed of MOy (where x