WAFER LEVEL PACKAGE, CHIP SIZE PACKAGE DEVICE AND METHOD OF MANUFACTURING WAFER LEVEL PACKAGE

Title:

WAFER LEVEL PACKAGE, CHIP SIZE PACKAGE DEVICE AND METHOD OF MANUFACTURING WAFER LEVEL PACKAGE

Document Type and Number:

WIPO Patent Application WO/2012/111174

Kind Code:

A1

Abstract:

A wafer level package (20A) according to the present invention is provided with a base wafer (22) having a plurality of semiconductor chips (1) mounted or formed on its surface and a cover wafer (23) opposite the base wafer (22). The base wafer (22) and the cover wafer (23) are joined so as to sandwich therebetween a frame-shaped seal frame (4) which seals the periphery of each semiconductor chip. A gap (24) is formed between respective seal frames (4) of mutually adjoining semiconductor chips (1). In the gap (24) between the respective seal frames (4) of the mutually adjoining semiconductor chips (1), a partial connect part (26) is provided, which mutually and partially connects both seal frames (4). Hereby, the occurrence of a crack in a seal frame can be avoided when dicing, while providing a wafer level package, a chip size package device and a method of manufacturing a wafer level package, which can suppress the occurrence of peel-off from a wafer even when a high-temperature process is applied after a wet process or after liquid cleaning.

More Like This:

JPH0547949

SEMICONDUCTOR DEVICE

Inventors:

OKUNO TOSHIAKI
INOUE KATSUYUKI
FUJIWARA TAKESHI
SEKI TOMONORI

Application Number:

PCT/JP2011/056237

Publication Date:

August 23, 2012

Filing Date:

March 16, 2011

Export Citation:

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Assignee:

OMRON TATEISI ELECTRONICS CO (JP)
OKUNO TOSHIAKI
INOUE KATSUYUKI
FUJIWARA TAKESHI
SEKI TOMONORI

International Classes:

H01L23/02

Foreign References:

JP2009004461A	2009-01-08
JP2008542578A	2008-11-27
JPH06318625A	1994-11-15
JP2003204005A	2003-07-18
US20090194861A1	2009-08-06

Other References: