WAFER LEVEL PACKAGING STRUCTURE OF HIGH-PIXEL IMAGE SENSOR CHIP

WIPO Patent Application WO/2016/184002

A1

A wafer level packaging structure of a high-pixel image sensor chip, comprising an image sensor chip (9) and a silicon substrate (1), wherein the image sensor chip comprises a basement (8), a sensing region (903) and several welding pads (902) located at the periphery of the sensing region; the silicon substrate has a first surface plane (101) and a second surface plane (102) opposite thereto, the second surface plane of the silicon substrate is pasted on a first surface of the basement, the silicon substrate is provided with an opening (2) penetrating through the silicon substrate at a position corresponding to the sensing region, the sensing region is exposed from the bottom of the opening; a light-transmitting substrate (7) is fixed on the top of the opening of the first surface plane of the silicon substrate, two surface planes of the light-transmitting substrate are parallel or approximately parallel to a plane where the sensing region is located, and a side wall of the opening is not perpendicular to the plane where the sensing region is located. The packaging structure reduces the influence of particles on the sensing region and reduces the influences of dazzling light, ghost, etc. produced by the high-pixel image sensor chip, and the steps for the packaging process are simple.

WAN LIXI (CN)
XIANG MIN (CN)
ZHAI LINGLING (CN)
QIAN JINGXIAN (CN)
MA LI (CN)

PCT/CN2015/090912

November 24, 2016

September 28, 2015

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HUATIAN TECH (KUNSHAN) ELECTRONICS CO LTD (CN)

H01L27/146

CN104795436A	2015-07-22
CN204680671U	2015-09-30
CN103972256A	2014-08-06
CN103985723A	2014-08-13
US20100007017A1	2010-01-14
US7459729B2	2008-12-02

KUN SHAN SIFANG PATENT OFFICE (CN)
昆山四方专利事务所 (CN)

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