Related Application

[001] The present invention claims priority to Singapore patent application no. 10202250273C filed on 23 June 2022, the disclosure of which is incorporated in its entirety.

Field of Invention

[002] The present invention relates to the fields of photonics and optoelectronics, such as optical communication, quantum communication, light detection and ranging, and bioimaging systems.

Background

[003] Waveguide integrated avalanche photodiode design has been reported in the publication titled as Monolithic Integrated InGaAs/InAlAs WDM-APDs With Partially Depleted Absorption Region and Evanescently Coupled Waveguide Structure (Y. Zhao et al., J. Light. Technol. 38(16), p. 4385): This work teaches about, high speed, highly sensitive, and P-down InGaAs/InAlAs avalanche photodiodes with evanescently coupled waveguide structure, wherein a partially depleted absorption region and tapered waveguide coupler are adopted. This work uses a III-V based waveguide.

[004] The publication titled as: 56GHz Waveguide Ge/Si Avalanche Photodiode (M. Huang et al., OFC, 2018, pp. 1-3) proposes a waveguide Ge/Si APD with ultra-high 3dB- bandwidths: 56GHz with a 1310nm responsivity of 1.08A/W and 36GHz with a 1310 nm responsivity of 6A/W. This work uses a Ge/Si substrate wherein the defects between the Ge/Si interface would hinder the device performance and there is scope to improve the absorption efficiency at short-wave infrared regime.

[005] InGaAs-based APDs are attracting more and more attention in light detection and ranging (LiDAR), quantum information, and bio-imaging applications in short-wave infrared (SWIR) regime, due to their high sensitivity, compact size, and moderate operation requirements [see refs. 1-3]. InGaAs-based APDs on the InP substrate has been reported [in ref. 6]. [006] There is a strong demand to enhance the performance of InGaAs-based APDs, including the responsivity, multiplication gain, dark current, and even single-photon counting characteristics.

Summary

[007] The following presents a simplified summary to provide a basic understanding of the present invention. This summary is not an extensive overview of the present invention, and is not intended to identify key features of the invention. Rather, it is to present some of the inventive concepts of this invention in a generalized form as a prelude to the detailed description that is to follow.

[008] According to a first aspect a waveguide-integrated avalanche photodiode (APD) is provided, comprising: an SOI substrate; a waveguide with a grating coupler formed on a silicon layer in the SOI substrate; an active APD device comprising a photonic absorption layer and a photonic multiplication layer, wherein the photonic absorption layer is bonded to the silicon layer via a bonding layer and is optically coupled to the waveguide, the photonic absorption layer comprising InGaAs compound and the photonic multiplication layer comprising a III-V compound; and a plurality of metal contacts such that in use an optical signal from the waveguide is converted to an electronic output signal of the integrated APD.

[009] Advantageously, under this invention, a) the hetero-integration of InGaAs-based APDs with silicon waveguide is shown to extend the absorption length to enhance the efficiency by separating the direction of light propagation and current flow, b) the light propagates along the silicon waveguide and is evanescently absorbed by the InGaAs layer on top, allowing the use of the InGaAs absorption layer with a small thickness and providing the advantages of higher operation speed and lower thermal generation noise in the InGaAs layer without the compromise of absorption efficiency, c) the invention integrates the silicon photonics and optoelectronics with silicon CMOS that shall enable large-scale on-chip optical communication and computing with miniaturized size, as well as high operation speed with low parasitics, d) with the integration on silicon the optical crosstalk of InGaAs- based APDs in an array will also be suppressed, since the secondary emitted photons can hardly transmit from the silicon substrate [see ref. 4]. The invention can be applied in the areas such as high-speed optical communication, detecting the returned light and ranging or LiDAR, quantum communication, and bio-imaging systems, e) the integration process is stable and repeatable with limited defects induced, f) good device uniformity is confirmed in the invention, g) the low temperature bonding process together with the outstanding performance enables this invention to pave way for an heterogeneous integration of such III- V APDs with optoelectronic or photonics based integrated circuits on silicon, and h) this integrated APD exhibits a high responsivity of substantially 0.99 AAV at substantially 1570 nm, a dark current (Idark) of substantially 7.6 nA at substantially 90% breakdown voltage (Vbr), and a maximum gain of substantially larger than 70.

[0010] According to an embodiment, the bonding layer comprises the photoresist SU-8. The bonding layer may be less than 150 nm which is advantageous in terms of topography. The good quality of the bonding showed promising performance of the fabricated waveguide-integrated APDs or ICs where the negligible variation induced by the bonding process has been confirmed. The low curing temperature of SU-8 and its relatively low volumetric shrinkage allows enhanced absorption efficiency without the compromise of the dark current (Idark).

[0011 ] According to an alternate embodiment, the bonding layer comprises AI2O3 that is deposited on the silicon layer and the absorption layer by atomic layer deposition (ALD). Advantageously, this is also a low temperature process.

[0012] According to an embodiment, the waveguide is tapered in a plan direction, and tapers out in the direction of the optical signal.

[0013] According to an embodiment, the multiplication layer comprises InAlAs. The temperature dependence of the invention relies on the impact ionization in InAlAs, which is mainly determined by the material property and is relatively small for InAlAs. Thus, the shift in the breakdown voltage of the invention against temperature is small enough, thereby delivering a robust performance. In addition, the integration process is stable and repeatable with limited defects induced. Good device uniformity is confirmed in the present invention.

[0014] According to an alternate embodiment, the multiplication layer comprises any one the following compounds: AlAsSb; GaAsSb; and InP. Regarding the general applicability, the method can be easily applied to most separate-absorption-charge-multiplication (SACM) based avalanche photodiodes operating at near-infrared or short-wave infrared regimes, including but not limited to Ge/Si APDs, InP/InGaAs APDs, InGaAs/AlAsSb APDs, and InGaAs/GaAsSb superlattice APDs by using similar integration and fabrication method.

[0015] The electric fields in the photonic multiplication layer and the photonic absorption layer may be designed by varying their doping profiles.

[0016] According to a second aspect, a silicon based integrated circuit comprising the waveguide integrated avalanche photodiode (APD) is provided.

[0017] According to a third aspect, a method of fabricating the waveguide-integrated avalanche photodiode (APD) comprising: forming a waveguide with a grating coupler on a silicon layer in a SOI substrate; forming a bonding layer on the silicon layer; bonding an active APD device on the silicon layer via the bonding layer, the active APD device comprising a photonic absorption layer and a photonic multiplication layer, such that the photonic absorption layer is bonded to the bonding layer and is optically coupled to the waveguide, the photonic absorption layer comprising InGaAs compound and the photonic multiplication layer comprising a III-V compound; forming a mesa structure of the active APD device by patterning and etching the InGaAs layer and the InAlAs layer; revealing the grating coupler and the waveguide by patterning and etching; forming a passivation; and forming and interconnecting a plurality of metal contacts such that in use an optical signal from the waveguide is converted to an electronic output signal of the integrated APD.

[0018] The method may comprise: forming the bonding layer by spin coating SU-8. Alternately, the method may comprise: forming the bonding layer by AI2O3 that is deposited on the silicon layer and the InGaAs layer by atomic layer deposition (ALD).

[0019] The method may further comprise: forming the active APD device by molecular beam epitaxial deposition of the photonic multiplication layer and the photonic absorption layer on an InP substrate; and etching the InP substrate after the bonding. The multiplication layer may comprise any one the following compounds: InAlAs, AlAsSb; GaAsSb; and InP.

[0020] The method may further comprise: baking the bonding layer with SU-8 at substantially 110 °C; exposing the bonding layer to UV rays to outgas; and curing the bonding layer at substantially 140 °C, for substantially 40 minutes. The method may further comprise: during the bonding, applying a pressure of around 40 N/cm ² on the active APD device.

[0021 ] Alternatively, the method may comprise: activating the bonding layer with AI2O3 in oxygen plasma; and during the bonding, applying a pressure of substantially 50 N/cm ² cm ² to 500 N/cm ² on the active APD device at substantially 300 °C for curing.

[0022] The method may further comprise: designing the electric fields in the photonic multiplication layer and the photonic absorption layer by tuning their doping profiles.

Brief Description of the Drawings

[0023] This invention will be described by way of non-limiting embodiments of the present invention, with reference to the accompanying drawings. The drawings are not to scale, instead emphasis is placed upon illustrating the principles of the invention. Herein:

[0024] Fig. 1 is a schematic illustration of an embodiment of the integrated avalanche photodiode (APD) with the InGaAs/InAlAs layers on a SOI substrate.

[0025] Fig. 2 is a 2D cross-sectional view of an embodiment of the integrated APD, along with the III-V layer structure.

[0026] Fig. 3 provides a Sentaurus simulation result of the E-field distribution in the InGaAs/InAlAs epi-layers on an InP substrate.

[0027] Figs. 4 to 9 in cross-sectional views illustrate the steps in forming the integrated APD with the InGaAs/InAlAs layers on the SOI substrate with a low-temperature bonding process followed by the InP substrate removal.

[0028] Fig. 10 presents the formation steps of the integrated APD in an embodiment.

[0029] Fig. 11 is a cross-sectional SEM image of the InGaAs/InAlAs layers on the SOI substrate for the integrated APD, showing the thin SU-8 of <150 nm and also the flat surfaces and sharp interfaces of the bonded layers. [0030] Fig. 12 shows a surface roughness RMS value of 1.39 nm that is obtained for the InGaAs/InAlAs epi-layers after the bonding and the handle InP substrate removal.

[0031 ] Fig. 13 shows the Lumerical simulation of the light transmission and absorption in the integrated APD.

[0032] Fig. 14 is a tilt-view SEM image of the integrated APD and the taper waveguide on the SOI substrate, wherein the inset is for the fabricated non-uniform grating coupler.

[0033] Fig. 15 shows the experimental setup for the integrated APD characterization, where the sample is placed in the probe station with a temperature control system.

[0034] Fig. 16 shows the I-V characteristics of the integrated APD under dark and at I of 1570 nm, wherein a low /dark of 7.6 nA is obtained at 90% Vbr-

[0035] Fig. 17 shows an I _p h as a function of Pm at I of 1570 nm, wherein the incident power is calibrated by the loss of the grating coupler.

[0036] Fig. 18 shows the multiplication gain of the integrated APD under various incident powers, wherein a maximum gain of >70 is achieved when Pin is -48.3 dBm.

[0037] Fig. 19 shows the temperature-dependent reverse bias I-V characteristics for the integrated APD within the wide temperature range of 180-293 K.

[0038] Fig. 20 shows an Arrhenius plot of /dark. EA of 0.297 eV that is extracted from the integrated APD while EA of 0.283 eV is from an APD on InP substrate.

[0039] Fig. 21 in a Table I is a benchmark of the reported APDs for SWIR detection, including InGaAs-based APDs on Si or InP substrate, Ge-on-Si APDs, and GeSn-based APDs.

Detailed Description

[0040] One or more specific and alternative embodiments of the present invention will now be described with reference to the attached drawings. It shall be apparent to one skilled in the art, however, that this invention may be practised without such specific details. Some of the details may not be described at length so as not to obscure the present invention. [0041 ] Figs. 1 and 2 show one embodiment of the silicon-waveguide-integrated InGaAs/InAlAs avalanche photodiode (APD) 100 on a silicon-on-insulator (SOI) substrate 20. The InGaAs layer 35 of the active APD device 95 is bonded to the SOI substrate 20. The InGaAs layer 35 is epitaxially deposited over a InAlAs layer 65. The metal contacts 75 make contact with the InGaAs layer 35, the InAlAs layer 65 and the SOI substrate 20. The interconnections of the metal contacts 75 are not shown. The grating coupler 16 and the silicon-taper waveguide 80 are fabricated on the SOI substrate 20 in order to input the optical signal under the InGaAs layer 35. The functioning of the silicon-taper waveguide 80 are well known in the art.

[0042] As shown, Fig. 2 is a 2D cross-sectional view of an embodiment of the silicon- waveguide-integrated InGaAs-based APD 100, along with the InGaAs/InAlAs layers 35, 65. All these InGaAs/InAlAs layers 35, 65 are grown by molecular beam epitaxy (MBE). As in the art, in this embodiment the SOI substrate 20 comprises of the silicon layer 15 deposited over a 3 um silicon buried oxide (BOX) 10 that is grown over a silicon substrate 5. The InGaAs layer 35 comprises of the 30nm p-InGaAs layer 25 under a lum unintentionally doped (uid) InGaAs layer 30. The InAlAs layer 65 comprises of a 60nm uid-InAlGaAs grading layer 40, a 113nm p-InAlAs layer 45, a 1pm uid-InAlAs layer 50, a 80nm n-InAlAs layer 55 and a 80nm uid-InAlAs layer 60. The lOOnm metal contact layer 70 is topped by the contact metal 75. The thicknesses of the layers as in this embodiment could be altered if required for any reason.

[0043] Fig. 3 provides a Sentaurus simulation result of the E-field distribution at the breakdown voltage Vbr in the epitaxially grown InGaAs/InAlAs layers 35, 65 on the InP substrate layer 85 as shown in Fig. 7. Simulations and extensive characterizations have been carried out to understand the performance of the active APD device 95 and to investigate the physical mechanisms before and after the bonding on the SOI substrate 20. The doping concentrations in the InGaAs/InAlAs layers 35, 65 as shown in Fig. 2 have been carefully designed to ensure the proper distribution of the electric field in both the InAlAs layer 65 for multiplication and in the InGaAs layer 35 for absorption.

[0044] Figs. 4 to 9 show the sequence of the fabrication process steps for formation of the InGaAs/ InAlAs layers 35, 65 on the SOI substrate 20. Both the InAlAs layer 65 and the InGaAs layer 35 are substantially 1-pm-thick each. The grating coupler 16 and the waveguide 80 that may be substantially 220 nm is formed in the silicon layer 15 by patterning and reactive ion etching. After the surface cleaning of the SOI substrate 20, a diluted SU-8 is spin-coated onto the fabricated SOI substrate 20 with a proper spin rate to obtain a final thickness of less than substantially 150 nm for the bonding layer 18, after bonding with the InGaAs layer 35. The coated sample is baked at substantially 110 °C, followed by an outgas by an UV exposure and curing at substantially 140 °C for substantially 40 minutes. The SU- 8 for the bonding layer 18 is interchangeable with an atomic layer deposition (ALD) AI2O3. The InGaAs/ InAlAs layers 35, 65 are epitaxially grown on an InP substrate 85. After the surface cleaning of the stack of the InGaAs/ InAlAs layers 35, 65 on the InP substrate 85, the stack is bonded on the SU-8 layer 18 by the InGaAs layer 35. During the bonding, a pressure of around 40 N/cm ² is applied. Once bonded to the SOI substrate 20, the InP substrate 85 is removed by concentrated HC1. If ALD deposited AI2O3 is used instead of SU-8, the AI2O3 will need to be deposited on both the SOI substrate 20 and the InGaAs layer 35. Then the activation will be done using oxygen plasma before the step of bonding. During bonding with the AI2O3, a pressure of substantially 50 N/cm ² to 500 N/cm ² may be applied at substantially 300 °C as the curing process.

[0045] Fig. 10 shows the key fabrication steps for the integrated APD 100. The grating coupler 16 with the waveguide 80 is formed by patterning and reactive ion etching (RIE). The photoresist SU-8 is spin coated on the silicon layer 15 followed by soft baking, and curing by UV exposure. The bonding is achieved by applying pressure over the InP substrate 85. The InP substrate 85 is then removed via wet etch by HCL: H2O. After the bonding of the InGaAs/InAlAs layers 35, 65 on the SOI substrate 20, the mesa structure for the APD device 95 is defined and patterned by wet etch with a mixture of H3PO4/H2O2/H2O wherein the mixture etches both the InGaAs layer 35 and the InAlAs layer 65. After the mesa formation, the APD device 95 is patterned and etched again to remove the InGaAs/InAlAs layers 35,65 at the peripheral region to reveal the grating coupler 16 and the waveguide 80 underneath. Thereafter, following passivation by a SU-8 coating, the metal is deposited by sputter. The metal contacts 75 are then patterned and formed by an inductively coupled plasma etching (ICP).

[0046] Fig. 11 is a cross-sectional SEM image of the InGaAs/InAlAs layers 35. ,65 on the SOI substrate 20 showing the thin bonding layer 18 of SU-8 of <150 nm and also the flat surfaces and sharp interfaces of the InGaAs/InAlAs layers 35, 65. The cross-sectional view of the bonded InGaAs/InAlAs layers 35, 65 on the SOI substrate 20 are shown where the flat layers and sharp interfaces are delineated. The surface roughness of the bonded wafer was checked by atomic force microscopy (AFM).

[0047] Fig. 12 shows a surface roughness of an RMS value of substantially 1.39 nm that is obtained for the epitaxially grown InGaAs/InAlAs layers 35, 65 after the bonding and the removal of the InP substrate 85.

[0048] Fig. 13 presents the simulated results of light transmission and absorption in the designed silicon- waveguide-integrated InGaAs-based APD 100. The simulation is conducted using Lumerical. Herein, most of the incident light is absorbed within the substantially 100-pm length. Accordingly, in the following experiments the integrated APD 100 has been designed with a length of substantially 100 pm and a width of substantially 12 pm.

[0049] Fig. 14 shows the tilt-view SEM images of the fabricated InGaAs-based APD device 95, and the tapered waveguide 80 on the SOI substrate 20, whilst an inset (b) shows the topview image for the fabricated non-uniform grating coupler 16.

[0050] Fig. 15 shows the experimental characterization setup for the integrated APD 100, where the integrated APD 100 is placed in a probe station 101 with a temperature control system 102. The manipulators 103 and the single-mode fibre 104 are connected for probing and illumination with the X-Y-Z controller 105. The illumination is fed to the fiber 104 from the tunable laser 107, via the grating coupler 16. The analyzer 106 receives inputs from the manipulator.

[0051 ] Fig. 16 shows the I-V characteristics of the integrated APD 100 as fabricated, without illumination measured at room temperature. The Vbr is measured as -62 V while the punch through occurs at around -47 V. A low dark current at substantially 90% Vbr of substantially 7.6 nA is obtained at room temperature. The I-V characteristics under illumination is then measured with the incident power ranging substantially from -33.3 dBm to -48.3 dBm (including the coupling loss from the grating coupler 16) at substantially 1570 nm. The photocurrent increases significantly after punch through and is then gradually multiplied until avalanche breakdown. [0052] Fig. 17 shows the extraction of the steady-state photo-responsivity of the waveguide- integrated APD 100 at unity gain. With the extended absorption length in the integrated APD 100 as enabled by the integration with the Si waveguide 80, a high responsivity of substantially 0.99 AAV is achieved at substantially 1570 nm, corresponding to a high external quantum efficiency (EQE) of substantially 78%.

[0053] Fig. 18 shows the multiplication gain of the integrated APD 100 as extracted under the illumination. A peak multiplication gain of substantially more than 70 is achieved at Vbias of substantially 59 V with incident power Pm of substantially -48.3 dBm. Increasing Pin reduces the peak avalanche gain of the integrated APD 100, since a larger P; _n leads to more photo-generated carriers in the InAlAs layer 65 for multiplication, reducing the electric field therein.

[0054] Fig. 19 shows the temperature dependence of the I-V characteristics that is substantially measured from 180 K to 293 K. The slight shift of Vbr can be observed when the temperature changes, indicating good temperature stability of the integrated APD 100. The dark current increases dramatically when the temperature increases, as the thermal generation becomes more severe.

[0055] Fig. 20 shows the results of further investigation of the generation mechanism in the integrated APD 100, with the plot of In (Idark at substantially 90%Vbr) vs. 1/kT. The data from InGaAs-based APDs on InP substrate (not shown) are plotted as well to make the comparison. The two curves exhibit a similar trend with tiny differences, indicating that the quality of the bonded InGaAs/InAlAs layers 35, 65 remains good and has no observable degradation induced by the bonding process. The activation energy (EA) of the Idark is extracted on both the APD 100 on SOI substrate 20 and the APD on InP substrates. The EA of substantially 0.297 eV is extracted for APD 100 on SOI substrate 20 while the EA of substantially 0.284 eV is extracted for that on the InP substrate. These values show good agreement with the reported works and indicate that the thermal generation in the InGaAs layer 35 for absorption is the dominant generation mechanism in both the APDs at such operating conditions.

[0056] Fig. 21 presents Table I that benchmarks the characteristics of reported APDs for SWIR detection, including InGaAs-based APDs on Si or InP substrate, Ge-on-Si APDs, and GeSn-based APDs [see references 5-11]. Even though Ge- or GeSn-based APDs have the advantages of direct growth on Si substrate, the high dark current is the main challenge. Compared to other InGaAs-based APDs, the APDs of the present invention provide advantages such as potentially easier integration with optoelectronic integrated circuits (OEIC) as well as the extended absorption length enabled by the integration with the Si waveguide for evanescent absorption. The present invention achieves a high responsivity of substantially 0.99 AAV at unity gain, a low dark current of substantially 7.6 nA at substantially 90% Vbr, and a maximum gain of substantially larger than 70.

[0057] References: [1] R. H. Hadfield, Nat. Photonics 3, p. 696, 2009. [2] C. Bruschini et al., Light Sci. Appl. 8, p. 1, 2019 [3] C. Yu et al., OE 25, p. 14611, 2017. [4] C. Niccolo et al., IEEE Photon. Technol. Lett. 28(16), p. 1767. [5] Y. Yuan et al., Opt. lett. 44(14), p. 3538. [6] Y. Zhao et al., J. Light. Technol. 38(16), p. 4385. [7] M. Nada et al., J. Light. Technol. 32(8), p. 1543. [8] J. Zhang et al., CLE02020, p. JTh2D-18. [9] M. Huang et al., ECOC2014. p. 1. [10] N. Duan et al., OE 20, pp. 11031-11036. [11] Y. Dong et al., IEDM 2015, p. 30- 5.

[0058] While specific embodiments have been described and illustrated, it is understood that many changes, modifications, variations and combinations of variations disclosed in the text description and drawings thereof could be made to the present invention without departing from the scope of the present invention.